TLK10232 datasheet(19/102 Pages) TI

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TLK10232

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SLLSEE1 – MAY 2013

Table 4-1. Specific Line Rate and Reference Clock Selection for the 1GBASE-KX Mode

LOW SPEED SIDE

HIGH SPEED SIDE

Line Rate

SERDES PLL

Rate

REFCLKP/N

Line Rate

SERDES PLL

Rate

REFCLKP/N

(Mbps)

Multiplier

(MHz)

(Mbps(1) )

Multiplier

(MHz)

3125(2)

Full

156.25

3125(2)

Full

156.25

3125(2)

Full

312.5

3125(2)

Full

312.5

1250

Half

125(2)

1250

Quarter

125(2)

1250

Half

156.25

1250

Quarter

156.25

1250

Quarter

312.5

1250

Quarter

312.5

(1)

High Speed Side SERDES runs at 2x effective data rate.

(2)

Manual mode only, as auto negotiation does not support 125Mhz REFCLK or line rate of 3125Mbps. To disable automatic setting of PLL

and rate modes, write 1'b1 to bit 13 of register 0x1E.001D.

4.5

Test Pattern Generator

In 1G-KX mode, this block can be used to generate test patterns allowing the 1G-KX channel to be tested

for compliance while in a system environment or for diagnostic purposes. Test patterns generated are

high/low/mixed frequency and CRPAT long or short.

4.6

Test Pattern Verifier

The 1G-KX test pattern verifier performs the verification and error reporting for the CRPAT Long and Short

test patterns specified in Annex 36A of the IEEE 802.3-2008 standard. Errors are reported to MDIO

registers.

4.7

1GBASE-KX Mode Latency

The latency through the TLK10232 in 1G-KX mode is as shown in Figure 4-2. Note that the latency ranges

shown indicate static rather than dynamic latency variance, i.e., the range of possible latencies when the

serial link is initially established. During normal operation, the latency through the device is fixed.

1GBASE-KX MODE FUNCTIONAL DESCRIPTION

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