TLK10232 datasheet(21/102 Pages) TI

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IN*3N

HSTX*P

HSTX*N

IN*3P

OUT*3N

HSRX*P

HSRX*N

OUT*3P

OUT*2N

OUT*2P

OUT*1N

OUT*1P

OUT*0N

OUT*0P

IN*2N

IN*2P

IN*1N

IN*1P

IN*0N

IN*0P

TLK10232

www.ti.com

SLLSEE1 – MAY 2013

GENERAL PURPOSE (10G) SERDES MODE FUNCTIONAL DESCRIPTION

A block diagram showing the transmit and receive data paths of the TLK10232 operating in General

Purpose (10G) SerDes mode is shown in Figure 5-1.

Figure 5-1. Block Diagram Showing General Purpose SerDes Mode

5.1

General Purpose SERDES Transmit Data Path

The TLK10232 General Purpose SERDES low speed to high speed (transmit) data path with the device

configured to operate in the normal transceiver (mission) mode is shown in the upper half of Figure 5-1. In

this mode, 8B/10B encoded serial data (IN*P/N) in 2 or 4 lanes is received by the low speed side

SERDES and deserialized into 10-bit parallel data for each lane. The data in each individual lane is then

byte aligned (channel synchronized) and then 8B/10B decoded into 8-bit parallel data for each lane. The

lane data is then lane aligned by the Lane Alignment Slave. 32 bits of lane aligned parallel data is input to

a transmit FIFO which delivers it to an 8B/10B encoder, 16 data bits at a time. The resulting 20-bit 8B/10B

encoded parallel data is sent to the high speed side SERDES for serialization and output through the

HSTX*P/N pins.

5.2

General Purpose SERDES Receive Data Path

With the device configured to operate in the normal transceiver (mission) mode, the high speed to low

speed (receive) data path is shown in the lower half of Figure 5-1. 8B/10B encoded serial data

(HSRX*P/N) is received by the high speed side SERDES and deserialized into 20-bit parallel data. The

data is then byte aligned, 8B/10B decoded into 16-bit parallel data, and then delivered to a receive FIFO.

The receive FIFO in turn delivers 32-bit parallel data to the Lane Alignment Master which splits the data

into the same number of lanes as configured on the transmit data path. The lane data is then 8B/10B

encoded and the resulting 10-bit parallel data for each lane is input to the low speed side SERDES for

serialization and output through the OUT*P/N pins.

GENERAL PURPOSE (10G) SERDES MODE FUNCTIONAL

DESCRIPTION

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