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TLK10232 Datasheet(PDF) 6 Page - Texas Instruments |
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TLK10232 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 102 page  TLK10232 SLLSEE1 – MAY 2013 www.ti.com 2.3 Terminal Functions The details of the terminal functions of the TLK10232 are provided in Table 2-1 and Table 2-2. Table 2-1. Pin Description - Signal Pins TERMINAL DIRECTION TYPE DESCRIPTION SIGNAL BGA SUPPLY CHANNEL A High Speed Transmit Channel A Output. HSTXAP and HSTXAN comprise the high HSTXAP D12 Output speed side transmit direction Channel A differential serial output signal. During device HSTXAN E12 CML VDDA_HS reset (RESET_N asserted low) these pins are driven differential zero. These CML outputs must be AC coupled. High Speed Receive Channel A Input. HSRXAP and HSRXAN comprise the high speed HSRXAP B12 Input side receive direction Channel A differential serial input signal. These CML input signals HSRXAN A12 CML VDDA_HS must be AC coupled. D1/E1 B2/C2 Input Low Speed Channel A Inputs. INAP and INAN comprise the low speed side transmit INA[3:0]P/N A1/B1 CML VDDA_LS direction Channel A differential input signals. These signals must be AC coupled. A4/A3 F3/E3 Low Speed Channel A Outputs. OUTAP and OUTAN comprise the low speed side C4/C5 Output OUTA[3:0]P/N receive direction Channel A differential output signals. During device reset (RESET_N B5/B6 CML VDDA_LS asserted low) these pins are driven differential zero. These signals must be AC coupled. A6/A7 Channel A Receive Loss Of Signal (LOS) Indicator. LOSA=0: Signal detected. LOSA=1: Loss of signal. Loss of signal detection is based on the input signal level. When HSRXAP/N has a differential input signal swing of ≤75 mVpp, LOSA will be asserted (if enabled). If the input signal is greater than 150 mVp-p, LOS will be deasserted. Outside of these ranges, the Output LVCMOS LOS indication is undefined. LOSA E9 1.5V/1.8V Other functions can be observed on LOSA real-time, configured via MDIO VDDO0 40 Ω Driver During device reset (RESET_N asserted low) this pin is driven low. During pin based power down (PDTRXA_N asserted low), this pin is floating. During register based power down, this pin is floating. It is highly recommended that LOSA be brought to an easily accessible point on the application board (header) in the event that debug is required. Channel A Receive Lane Alignment Status Indicator. Lane alignment status signal received from a Lane Alignment Slave on the link partner Input LVCMOS LS_OK_IN_A B10 device. Valid in 10G General Purpose Serdes Mode. 1.5V/1.8V VDDO0 LS_OK_IN_A=0: Channel A link partner receive lanes not aligned. LS_OK_IN_A=1: Channel A link partner receive lanes aligned Channel A Transmit Lane Alignment Status Indicator. Output LVCMOS Lane alignment status signal sent to a Lane Alignment Master on the link partner device. LS_OK_OUT_A D9 1.5V/1.8V Valid in 10G General Purpose Serdes Mode. VDDO0 40 Ω Driver LS_OK_OUT_A=0: Channel A link partner transmit lanes not aligned. LS_OK_OUT_A=1: Channel A link partner transmit lanes aligned. Transceiver Power Down. Input LVCMOS When this pin is held low (asserted), Channel A is placed in power down mode. When PDTRXA_N A8 1.5V/1.8V VDDO0 deasserted, Channel A operates normally. After deassertion, a software data path reset should be issued through the MDIO interface. CHANNEL B High Speed Transmit Channel B Output. HSTXBP and HSTXBN comprise the high HSTXBP K12 Output CML speed side transmit direction Channel B differential serial output signal. During device HSTXBN L12 VDDA_HS reset (RESET_N asserted low) these pins are driven differential zero. These CML outputs must be AC coupled. High Speed Receive Channel B Input. HSRXBP and HSRXBN comprise the high speed HSRXBP H12 Input CML side receive direction Channel B differential serial input signal. These CML input signals HSRXBN G12 VDDA_HS must be AC coupled. M3/M4 L1/M1 Input CML Low Speed Channel B Inputs. INBP and INBN comprise the low speed side transmit INB[3:0]P/N K2/L2 VDDA_LS direction Channel B differential input signals. These signals must be AC coupled. H1/J1 M7/M6 Low Speed Channel B Outputs. OUTBP and OUTBN comprise the low speed side L6/L5 Output CML OUTB[3:0]P/N receive direction Channel B differential output signals. During device reset (RESET_N K5/K4 VDDA_LS asserted low) these pins are driven differential zero. These signals must be AC coupled. J3/H3 6 Physical Characteristics Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLK10232 |
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