TLK10232 datasheet(8/102 Pages) TI

8 / 102 page

TLK10232

SLLSEE1 – MAY 2013

www.ti.com

Table 2-1. Pin Description - Signal Pins (continued)

TERMINAL

DIRECTION

TYPE

DESCRIPTION

SIGNAL

BGA

SUPPLY

MDIO Port Address. Used to select the MDIO port address.

PRTAD[4:1] selects the MDIO port address. The TLK10232 has two different MDIO port

addresses. Selecting a unique PRTAD[4:1] per TLK10232 device allows 16 TLK10232

devices per MDIO bus. Each channel can be accessed by setting the appropriate port

address field within the serial interface protocol transaction.

Input LVCMOS

The TLK10232 will respond if the 4 MSB’s of the port address field on MDIO protocol

PRTAD[4:0]

1.5V/1.8V VDDO[1:0]

(PA[4:1]) matches PRTAD[4:1].

If PA[0] = 1’b0, TLK10232 Channel A will respond.

E10

If PA[0] = 1’b1, TLK10232 Channel B will respond.

PRTAD0 is not needed for port addressing, but can be used as a general purpose input

pin to control the switching function or the stopwatch latency measurement. If these

functions are not needed, PRTAD0 should be grounded on the application board.

Input LVCMOS

Low True Device Reset. RESET_N must be held asserted (low logic level) for at least

RESET_N

1.5V/1.8V VDDO01

10us after device power stabilization.

Input LVCMOS

MDIO Clock Input. Clock input for the MDIO interface.

MDC

with Hysteresis

Note that an external pullup is generally not required on MDC except if driven by an open-

1.5V/1.8V VDDO1

drain/open-collector clock source.

MDIO Data I/O. MDIO interface data input/output signal for the MDIO interface. This

signal must be externally pulled up to VDDO using a 2k

Ω resistor.

During device reset (RESET_N asserted low) this pin is floating. During software initiated

Input/ Output

power down the management interface remains active for control register writes and

MDIO

LVCMOS 1.5V/1.8V

reads. Certain status bits will not be deterministic as their generating clock source may be

VDDO1 25

Ω Driver

disabled as a result of asserting either power down input signal. During pin based power

down (PDTRXA_N and PDTRXB_N asserted low), this pin is floating. During register

based power down, this pin is driven normally.

JTAG Input Data. TDI is used to serially shift test data and test instructions into the

Input LVCMOS

device during the operation of the test port. In system applications where JTAG is not

TDI

1.5V/1.8V VDDO0

implemented, this input signal may be left floating.

(Internal Pullup)

During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is not

pulled up. During register based power down, this pin is pulled up normally.

JTAG Output Data. TDO is used to serially shift test data and test instructions out of the

device during operation of the test port. When the JTAG port is not in use, TDO is in a

Output LVCMOS

high impedance state.

TDO

1.5V/1.8V VDDO0

During device reset (RESET_N asserted low) this pin is floating. During pin based power

Ω Driver

down (PDTRXA_N and PDTRXB_N asserted low), this pin is not pulled up. During

JTAG Mode Select. TMS is used to control the state of the internal test-port controller. In

Input LVCMOS

system applications where JTAG is not implemented, this input signal can be left

TMS

1.5V/1.8V VDDO0

unconnected.

(Internal Pullup)

During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is not

pulled up. During register based power down, this pin is pulled up normally.

Input LVCMOS

JTAG Clock. TCK is used to clock state information and test data into and out of the

TCK

with Hysteresis

device during boundary scan operation. In system applications where JTAG is not

1.5V/1.8V VDDO0

implemented, this input signal should be grounded.

JTAG Test Reset. TRST_N is used to reset the JTAG logic into system operational

mode. This input can be left unconnected in the application and is pulled down internally,

Input LVCMOS

disabling the JTAG circuitry. If JTAG is implemented on the application board, this signal

TRST_N

1.5V/1.8V VDDO0

should be deasserted (high) during JTAG system testing, and otherwise asserted (low)

(Internal Pulldown)

during normal operation mode.

During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is not

pulled up. During register based power down, this pin is pulled up normally.

Test Enable. This signal is used during the device manufacturing process. It should be

Input LVCMOS

grounded through a resistor in the device application board. The application board should

TESTEN

L10

1.5V/1.8V VDDO1

allow the flexibility of easily reworking this signal to a high level if device debug is

necessary (by including an uninstalled resistor to VDDO).

General Purpose Input. This signal is used during the device manufacturing process. It

Input LVCMOS

should be grounded through a resistor on the device application board. The application

GPI0

J10

1.5V/1.8V VDDO1

board should also allow the flexibility of easily reworking this signal to a high level if

device debug is necessary (by including an uninstalled resistor to VDDO).

SERDES Channel A Analog Testability I/O. This signal is used during the device

AMUXA

C11

Analog I/O

manufacturing process. It should be left unconnected in the device application.

SERDES Channel B Analog Testability I/O. This signal is used during the device

AMUXB

Analog I/O

manufacturing process. It should be left unconnected in the device application.

Physical Characteristics

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