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TLK10232 Datasheet(PDF) 4 Page - Texas Instruments

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Part # TLK10232
Description  DUAL-CHANNEL XAUI/10GBASE-KR TRANSCEIVER WITH CROSSPOINT
PDF  102 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TLK10232 Datasheet(HTML) 4 Page - Texas Instruments

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CLOCKS
DATA PATH
(Channel A)
CONTROL,
STATUS, TEST
High
Speed
Outputs
High
Speed
Inputs
Low
Speed
Outputs
Low
Speed
Inputs
MDIO
JTAG
INA0P/N
INA1P/N
INA2P/N
INA3P/N
OUTA0P/N
OUTA1P/N
OUTA2P/N
OUTA3P/N
HSTXAP/N
HSRXAP/N
REFCLK0P/N
REFCLK1P/N
REFCLK_SEL
CLKOUTAP/N
LS_OK_IN_A
LS_OK_OUT_A
PDTRX_N
RESET_N
TESTEN
PRBSEN
PRBS_PASS
GPI0
LOSA
PRTAD[4:0]
MDC
MDIO
ST
MODE_SEL
TDO
TMS
TRST_N
TCK
TDI
TLK10232
SLLSEE1 – MAY 2013
www.ti.com
2
Physical Characteristics
2.1
Block Diagram
Various interfaces of the TLK10232 device are shown in Figure 2-1 for Channel A. The implementation is
the same for Channel B. A simplified one-channel block diagram of both the transmit and recive data path
is shown in Figure 2-2. This low-power transceiver consists of two serializer/deserializer (SERDES)
blocks, one on the low speed side and the other on the high speed side. The core logic block that lies
between the two SERDES blocks carries out all the logic functions including channel synchronization, lane
alignment, 8B/10B and 64B/66B encoding/decoding, as well as test pattern generation and verification.
The TLK10232 provides a management data input/output (MDIO Clause 22/45) interface as well as a
JTAG interface for device configuration, control, and monitoring. Detailed description of the TLK10232 pin
functions is provided in Table 2-1.
Figure 2-1. TLK10232 Interfaces
4
Physical Characteristics
Copyright © 2013, Texas Instruments Incorporated
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