TLK10232 datasheet(53/102 Pages) TI

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TLK10232

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SLLSEE1 – MAY 2013

Table 8-24. CLK_CONTROL(1) (continued)

Device Address: 0x1E SPACER Register Address:0x000D SPACER Default: 0x2F80

Bit(s)

Name

Description

Access

CLKOUT Output clock divide setting. This value is used to divide selected clock

(Selected using CLKOUT_SEL) before giving it out onto respective channel

CLKOUTx_P/N.

0000 = Divide by 1

0001 = RESERVED

0010 = RESERVED

0011 = RESERVED

0100 = Divide by 2

0101 = RESERVED

CLKOUT_DIV[3:0]

7:4

0110 = RESERVED

(RXG)

0111 = RESERVED

1000 = Divide by 4 (Default 4'b1000)

1001 = Divide by 8

1010 = Divide by 16

1011 = RESERVED

1100 = Divide by 5

1101 = Divide by 10

1110 = Divide by 20

1111 = Divide by 25

CLKOUT Output clock select. Selects Recovered clock sent out on CLKOUTx_P/N

pins (Default 4'b0000)

00x0 = Selects Ch A HS recovered byte clock as output clock

00x1 = Selects Ch A HS transmit byte clock as output clock

010x = Selects Ch A HSRX VCO divide by 4 clock as output clock

CLKOUT_SEL[3:0]

0110 = Selects Ch A LS recovered byte clock as output clock

3:0

(RXG)

0111 = Selects Ch A LS transmit byte clock as output clock

10x0 = Selects Ch B HS recovered byte clock as output clock

10x1 = Selects Ch B HS transmit byte clock as output clock

110x = Selects Ch B HSRX VCO divide by 4 clock as output clock

1110 = Selects Ch B LS recovered byte clock as output clock

1111 = Selects Ch B LS transmit byte clock as output clock

Table 8-25. RESET_CONTROL

Device Address: 0x1E SPACERRegister Address:0x000E SPACERDefault:0x0000

Bit(s)

Name

Description

Access

15:8

RESERVED

For TI use only. Always reads 0.

7:4

RESERVED

For TI use only. (Default 4'b0000)

Channel datapath reset control. Required once the desired functional mode is

configured.

DATAPATH_RESET

0 = Normal operation. (Default 1’b0)

(RXG)

1 = Resets channel logic excluding MDIO registers. (Resets both Tx and Rx

datapath)

Transmit FIFO reset control. Applicable in 10G mode only. Not required in

TXFIFO_RESET

10GKR mode as 10GKR FIFO is self centering.

SC(1)

(G)

0 = Normal operation. (Default 1’b0)

1 = Resets transmit datapath FIFO.

Receive FIFO reset control. Applicable in 10G mode only. Not required in

RXFIFO_RESET

10GKR mode as 10GKR FIFO is self centering.

(G)

0 = Normal operation. (Default 1’b0)

1 = Resets receive datapath FIFO.

RESERVED

For TI use only. (Default 1'b0)

(1)

After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle.

DEVICE REGISTERS

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