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TLK10232 Datasheet(PDF) 73 Page - Texas Instruments

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Part # TLK10232
Description  DUAL-CHANNEL XAUI/10GBASE-KR TRANSCEIVER WITH CROSSPOINT
PDF  102 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TLK10232 Datasheet(HTML) 73 Page - Texas Instruments

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TLK10232
www.ti.com
SLLSEE1 – MAY 2013
Table 8-87. KR_VS_CTC_ERR_CODE_LN3
Device Address: 0x01 SPACER Register Address: 0x8008 SPACER Default: 0x0080
Acces
Bit(s)
Name
Description
s
Applicable in 10G-KR mode only. XGMII code to be transmitted in case of
error condition. This applies to both TX and RX data paths. The msb is the
KR_CTC_ERR_CODE_LN3
15:7
control bit; remaining 8 bits constitute the error code. The default value for
RW
(R)
lane 3 corresponds to 8’h01 with the control bit being 1’b0. The default
values for lanes 0~3 correspond to ||LF||
6:0
RESERVED
For TI use only. Always reads 0.
RW
Table 8-88. KR_VS_LN0_EOP_ERROR_COUNTER
Device Address: 0x01 SPACER Register Address: 0x8010 SPACER Default: 0xFFFD
Bit(s)
Name
Description
Access
15:0
KR_LN0_EOP_ERR_COUNT Lane 0 End of packet Error counter.
(R)
End of packet error is detected when Terminate character is in lane 0 and one or
both of the following holds:
COR
●Terminate character is not followed by /K/ characters in lanes 1, 2 and 3
●The column following the terminate column is neither ||K|| nor ||A||.
Counter value cleared to 16’h0000 when read.
Table 8-89. KR_VS_LN1_EOP_ERROR_COUNTER
Device Address: 0x01 SPACER Register Address: 0x8011 SPACER Default: 0xFFFD
Bit(s)
Name
Description
Access
15:0
KR_LN1_EOP_ERR_COUN
Lane 1 End of packet Error counter.
T
End of packet error is detected when Terminate character is in lane 1 and one or
(R)
both of the following holds:
COR
● Terminate character is not followed by /K/ characters in lanes 2 and 3
● The column following the terminate column is neither ||K|| nor ||A||.
Counter value cleared to 16’h0000 when read.
Table 8-90. KR_VS_LN2_EOP_ERROR_COUNTER
Device Address: 0x01 SPACER Register Address: 0x8012 SPACER Default: 0xFFFD
Bit(s)
Name
Description
Access
15:0
KR_LN2_EOP_ERR_COU
Lane 2 End of packet Error counter.
NT
End of packet error is detected when Terminate character is in lane 2 and one or
(R)
both of the following holds:
COR
● Terminate character is not followed by /K/ characters in lane 3
● The column following the terminate column is neither ||K|| nor ||A||.
Counter value cleared to 16’h0000 when read.
Table 8-91. KR_VS_LN3_EOP_ERROR_COUNTER
Device Address: 0x01 SPACER Register Address: 0x8013 SPACER Default: 0xFFFD
Bit(s)
Name
Description
Access
15:0
KR_LN3_EOP_ERR_COUNT
Lane 3 End of packet Error counter.
COR
(R)
End of packet error is detected when Terminate character is in lane 3 and the
column following the terminate column is neither ||K|| nor ||A||. Counter value
cleared to 16’h0000 when read.
Copyright © 2013, Texas Instruments Incorporated
DEVICE REGISTERS
73
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