PCM1861 datasheet(49/115 Pages) TI

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1.4 V

LRDO

BCK

LRCK

0.5 V

DOUT

LRCP

BCKH

BCKL

LRHD

LRSU

BCKP

CKDO

PCM1861, PCM1863, PCM1865

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SLAS831C – MARCH 2014 – REVISED AUGUST 2014

Audio Format Selection and Timing Details (continued)

8.21.5.1 Interface Timing

Figure 45 and Figure 46 illustrate the interface timing in slave mode, and Figure 47 shows master mode.

PARAMETER(1)

MIN

TYP

MAX

UNIT

tBCKP

BCK Period

1/(64fS)

tBCKH

BCK Pulse Width HIGH

1.5 × tSCKI

tBCKL

BCK Pulse Width LOW

1.5 × tSCKI

tLRSU

LRCK Set Up Time to BCK Rising Edge

tLRHD

LRCK Hold Time to BCK Rising Edge

tLRCP

LRCK Period

µs

tCKDO

Delay time BCK Falling Edge to DOUT Valid

–10

tLRDO

Delay time LRCK Edge to DOUT Valid

–10

Rise Time of All Signals

Fall Time of All Signals

(1)

Timing measurement reference level is 1.4V for input and 0.5VDD for output. Rise and fall times are measured from 10% to 90% of the

IN/OUT signals' swing. Load capacitance of DOUT is 20pF. tSCKI means SCKI period.

spacer

Figure 45. Audio Data Interface Timing (Slave Mode: LRCK and BCK work as inputs)

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PCM1861 Datasheet(PDF) 49 Page - Texas Instruments

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