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PCM1861 Datasheet(PDF) 85 Page - Texas Instruments |
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PCM1861 Datasheet(HTML) 85 Page - Texas Instruments |
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85 / 115 page ![]() PCM1861, PCM1863, PCM1865 www.ti.com SLAS831C – MARCH 2014 – REVISED AUGUST 2014 RSV Reserved Reserved. Do not access. DIV_NUM[6:0] Set the ADC Clock Divider Value Ignored if CLKDET_EN = 1 Default value: 0000011 0: 1 1: 1/2 2: 1/3 3: 1/4 : : 127: 1/128 Page 0 / Register 37 (Hex 0x25) Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 37 0x25 RSV DIV_NUM6 DIV_NUM5 DIV_NUM4 DIV_NUM3 DIV_NUM2 DIV_NUM1 DIV_NUM0 Reset Value 0 0 0 0 0 1 1 1 RSV Reserved Reserved. Do not access. DIV_NUM[6:0] Set the PLL SCK Clock Divider value Default value: 0000111 Divider value. 0: 1 1: 1/2 2: 1/3 3: 1/4 : : 7: 1/8 (Default) : : 127: 1/128 Page 0 / Register 38 (Hex 0x26) Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 38 0x26 RSV DIV_NUM6 DIV_NUM5 DIV_NUM4 DIV_NUM3 DIV_NUM2 DIV_NUM1 DIV_NUM0 Reset Value 0 0 0 0 0 0 1 1 RSV Reserved Reserved. Do not access. DIV_NUM[6:0] Set the Master Clock (SCK) Divider value Ratio of Master clock (SCK) to Bit Clock (BCK) Default value: 0000011 Divider value. 0: 1 1: 1/2 2: 1/3 3: 1/4 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 85 Product Folder Links: PCM1861 PCM1863 PCM1865 |
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