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PCM1861 Datasheet(PDF) 67 Page - Texas Instruments |
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PCM1861 Datasheet(HTML) 67 Page - Texas Instruments |
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67 / 115 page  PCM1861, PCM1863, PCM1865 www.ti.com SLAS831C – MARCH 2014 – REVISED AUGUST 2014 12 Programming and Registers Reference 12.1 Coefficient Data Formats All mixer gain coefficients are 24-bit coefficients using a 4.20 number format. Numbers formatted as 4.20 numbers have 4 bits to the left of the binary point and 20 bits to the right of the binary point. If the most significant bit is logic 0, the number is a positive number. If the most significant bit is a logic 1, then the number is a negative number. In this case, every bit must be inverted, a 1 added to the result. See SLAC663. 12.2 Register Map The register map is the primary way to configure the PCM186x software programmable devices. The register map is separated into four pages (Page 0,1,3 and 253). Page 0 handles all of the device configuration whilst Page 1 is used to indirectly program coefficients into the two fixed function DSPs on the IC. Page 3 contains some additional registers for lower power usage along with Page 253. All undocumented registers should be considered reserved and should not be written. Changing between pages is done by writing to register 0x00 with the page that you want. Resetting registers is done by writing 0xFF to register 0x00. 12.2.1 Register Map Summary Register Map Summary Page 0 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 1 0x01 PGA_VAL_CH1_L PGA_VAL_CH1_L PGA_VAL_CH1_L PGA_VAL_CH1_L PGA_VAL_CH1_L PGA_VAL_CH1_L PGA_VAL_CH1_L PGA_VAL_CH1_L 7 6 5 4 3 2 1 0 2 0x02 PGA_VAL_CH1_ PGA_VAL_CH1_ PGA_VAL_CH1_ PGA_VAL_CH1_ PGA_VAL_CH1_ PGA_VAL_CH1_ PGA_VAL_CH1_ PGA_VAL_CH1_ R7 R6 R5 R4 R3 R2 R1 R0 3 0x03 PGA_VAL_CH2_L RSV RSV RSV RSV RSV RSV RSV 4 0x04 PGA_VAL_CH2_ PGA_VAL_CH2_ PGA_VAL_CH2_ PGA_VAL_CH2_ PGA_VAL_CH2_ PGA_VAL_CH2_ PGA_VAL_CH2_ PGA_VAL_CH2_ R7 R6 R5 R4 R3 R2 R1 R0 5 0x05 SMOOTH LINK DPGA_CLIP_EN MAX_ATT1 MAX_ATT0 START_ATT1 START_ATT0 AGC_EN 6 0x06 POL RSV SEL_L5 SEL_L4 SEL_L3 SEL_L2 SEL_L1 SEL_L0 7 0x07 POL RSV SEL_R5 SEL_R4 SEL_R3 SEL_R2 SEL_R1 SEL_R0 8 0x08 POL RSV SEL_L5 SEL_L4 SEL_L3 SEL_L2 SEL_L1 SEL_L0 9 0x09 POL RSV SEL_R5 SEL_R4 SEL_R3 SEL_R2 SEL_R1 SEL_R0 10 0x0A RSV RSV RSV RSV SEL3 SEL2 SEL1 SEL0 11 0x0B RX_WLEN1 RX_WLEN0 RSV TDM_LRCK_MO TX_WLEN1 TX_WLEN0 FMT1 FMT0 DE 12 0x0C RSV RSV RSV RSV RSV RSV TDM_OSEL1 TDM_OSEL0 13 0x0D TX_TDM_OFFSE TX_TDM_OFFSE TX_TDM_OFFSE TX_TDM_OFFSE TX_TDM_OFFSE TX_TDM_OFFSE TX_TDM_OFFSE TX_TDM_OFFSE T7 T6 T5 T4 T3 T2 T1 T0 14 0x0E RX_TDM_OFFSE RX_TDM_OFFSE RX_TDM_OFFSE RX_TDM_OFFSE RX_TDM_OFFSE RX_TDM_OFFSE RX_TDM_OFFSE RX_TDM_OFFSE T7 T6 T5 T4 T3 T2 T1 T0 15 0x0F DPGA_VAL_CH1 DPGA_VAL_CH1 DPGA_VAL_CH1 DPGA_VAL_CH1 DPGA_VAL_CH1 DPGA_VAL_CH1 DPGA_VAL_CH1 DPGA_VAL_CH1 _L7 _L6 _L5 _L4 _L3 _L2 _L1 _L0 16 0x10 GPIO1_POL GPIO1_FUNC2 GPIO1_FUNC1 GPIO1_FUNC0 GPIO0_POL GPIO0_FUNC2 GPIO0_FUNC1 GPIO0_FUNC0 17 0x11 GPIO3_POL GPIO3_FUNC2 GPIO3_FUNC1 GPIO3_FUNC0 GPIO2_POL GPIO2_FUNC2 GPIO2_FUNC1 GPIO2_FUNC0 18 0x12 GPIO1_DIR2 GPIO1_DIR1 GPIO1_DIR0 RSV GPIO0_DIR2 GPIO0_DIR1 GPIO0_DIR0 19 0x13 GPIO3_DIR2 GPIO3_DIR1 GPIO3_DIR0 RSV GPIO2_DIR2 GPIO2_DIR1 GPIO2_DIR0 20 0x14 GPIO3_OUT GPIO2_OUT GPIO1_OUT GPIO0_OUT GPIO3_IN GPIO2_IN GPIO1_IN GPIO0_IN 21 0x15 PULL_DOWN_DI PULL_DOWN_DI PULL_DOWN_DI PULL_DOWN_DI RSV RSV RSV RSV S[3] S[2] S[1] S[0] 22 0x16 DPGA_VAL_CH1 DPGA_VAL_CH1 DPGA_VAL_CH1 DPGA_VAL_CH1 DPGA_VAL_CH1 DPGA_VAL_CH1 DPGA_VAL_CH1 DPGA_VAL_CH1 _R7 _R6 _R5 _R4 _R3 _R2 _R1 _R0 23 0x17 DPGA_VAL_CH2 DPGA_VAL_CH2 DPGA_VAL_CH2 DPGA_VAL_CH2 DPGA_VAL_CH2 DPGA_VAL_CH2 DPGA_VAL_CH2 DPGA_VAL_CH2 _L7 _L6 _L5 _L4 _L3 _L2 _L1 _L0 24 0x18 DPGA_VAL_CH2 DPGA_VAL_CH2 DPGA_VAL_CH2 DPGA_VAL_CH2 DPGA_VAL_CH2 DPGA_VAL_CH2 DPGA_VAL_CH2 DPGA_VAL_CH2 _R7 _R6 _R5 _R4 _R3 _R2 _R1 _R0 25 0x19 DPGA_CH2_R DPGA_CH2_L DPGA_CH1_R DPGA_CH1_L APGA_CH2_R APGA_CH2_L APGA_CH1_R APGA_CH1_L 26 0x1A DIGMIC_IN1_SEL DIGMIC_IN1_SEL DIGMIC_IN0_SEL DIGMIC_IN0_SEL RSV RSV DIGMIC_4CH DIGMIC_EN 1 0 1 0 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 67 Product Folder Links: PCM1861 PCM1863 PCM1865 |
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