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PCM1861 Datasheet(PDF) 18 Page - Texas Instruments |
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PCM1861 Datasheet(HTML) 18 Page - Texas Instruments |
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18 / 115 page  Mix & Mux Mix & Mux Audio ADC Audio ADC DSP#1 DSP#2 Digital Mic Inputs Analog PGA Digital PGA FIR/IIR Filter PGA Zero Cross Detect SEC ADC 6ch Mixer (ADC + I2S) Digital S-Curve Volume Digital Zero Crossing Detect Energysense Signal Loss LPF HPF Energysense Signal Resume DC Threshold Cross Detect HPF Interrupt Manager and Controller Audio Serial TX Audio Serial RX 6ch Audio Serial TX DOUT DOUT2 (GPIO) DIN (GPIO) On Chip Oscillator 1/8 ADC Master Clock Clock Generator & Detector PLL Onchip Oscillator SCKI XTI(XTAL) Mux XTO(XTAL) Mux BCK_IN Audio ADC Audio ADC PGA Controller Analog CTRL 6ch 2ch BCK LRCK SCKO (GPIO) INT I2C/SPI Port Mic Bias Mic Bias VINL4 (4M) VINL3 (4P) VINL2 (1M) VINL1 (1P) VINR1 (2P) VINR2 (2M) VINR4 (3M) VINR3 (3P) GPIO2 / INT B / DMCLK GPIO1 / INT-A / DMIN MISO / GPIO0 / DMIN2 PCM1861, PCM1863, PCM1865 SLAS831C – MARCH 2014 – REVISED AUGUST 2014 www.ti.com 8 Detailed Description 8.1 Overview 64×fS (32×fS support in software controlled • Advanced Clocking support devices) – External XTAL support for Master Mode • Secondary ADC can be used for control signals – External CMOS Master Clock Support for – Measure External DC voltages such as control Master Mode potentiometers – Integrated PLL for generating audio clocks – Generate Interrupts on programmable from any BCK/MCK Source. thresholds – Device can output Audio Master Clock when • Extensive Interrupt Sources running from Non-Audio Master Clock, for use with other converters. Device must be in 8.2 Functional Block Diagram Master mode for this function. An internal block diagram of the PCM186x family is – BCK PLL available to avoid using External shown below. Note that power supplies and SCK references have been omitted from this diagram to – Clock (SCK, BCK, LRCK) Error Detection with aid simplicity. Smart Mute – BIT Clock (BCK) for PLL Reference: 48×fS or Figure 19. Internal Block Diagram of the PCM186x 8.3 Terminology Control registers in this datasheet are given by REGISTER BIT/BYTE NAME (Page.x HEX ADDRESS).. SE refers to "Single Ended" analog inputs, DIFF refers to "Differential" analog inputs. SCK (System Clock) and MCLK (Master Clock) are used interchangeably. Sampling frequency is symbolized by "fS". Full scale is symbolized by "FS". Sample time as a unit is symbolized by "tS". 18 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: PCM1861 PCM1863 PCM1865 |
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