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PCM1861 Datasheet(PDF) 32 Page - Texas Instruments |
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PCM1861 Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 115 page  PCM1861, PCM1863, PCM1865 SLAS831C – MARCH 2014 – REVISED AUGUST 2014 www.ti.com 8.13.4.4 PCM186x BCK Input Slave PLL Mode The PCM186x software programmable devices can generate an internal MCLK system clock using it’s PLL (referenced from an external input BCK) in slave mode. BCK must be 64fS. Supported sampling frequencies are listed in Table 11. Whilst the PCM186x can support down to 8kHz, analog performance is not tested at this rate. Table 11. Auto PLL BCK Requirements Sampling Frequency BCK Ratio to LRCK BCK Frequency 8kHz 256 2.048 16kHz 64 1.024 256 4.096 48kHz 32 1.536 48 2.304 64 3.072 256 12.288 96kHz 32 3.072 48 4.608 64 6.144 256 24.576 192kHz 32 6.144 48 9.216 64 12.288 256 49.152 In software SPI/I2C mode, a PCM186x software programmable device can use its on-chip crystal oscillator, if a CMOS clock source is not available. Audio Clocks can be generated through the PLL from the non-audio standard CMOS/Crystal frequency (and then can be divided down as described above). This function is not available in hardware mode. 8kHz is only supported if an external MCK is provided. The Autodetect and PLL system support frequencies as low as 32kHz. Analog performance is not tested in this mode. The clock tree can also be programmed manually, with the settings shown in Table 12. Table 12. 1863 (2ch) PLL BCK Settings fS BCK BCK PLL PLL PLL DSP1 DSP1 DSP 2 DSP2 ADC ADC Ratio Freq. Ratio Frequenc Configur Clock Clock Clock Clock Clock Clock (MHz) y (MHz) ation (MHz) Divider 2 (MHz) Divider (MHz) Divider 2CH CH Mode Source Divider Source Divider Source Divider 8 kHz 256 2.048 12288 98.304 P=0,R=1, 2.048 PLL 48 2.048 PLL 48 1.024 PLL 96 J=24, D=0 16 kHz 64 1.024 6144 98.304 P=0,R=1, 4.096 PLL 24 4.096 PLL 24 2.048 PLL 48 J=48, D=0 256 4.096 6144 98.304 P=1,R=1, 4.096 PLL 24 4.096 PLL 24 2.048 PLL 48 J=24, D=0 48 kHz 32 1.536 2048 98.304 P=0,R=1, 12.288 PLL 8 12.288 PLL 8 6.144 PLL 16 J=32, D=0 48 2.304 2048 92.16 P=0,R=1, 15.36 PLL 6 15.36 PLL 6 6.144 PLL 15 J=20, D=0 64 3.072 2048 98.304 P=0,R=1, 12.288 PLL 8 12.288 PLL 8 6.144 PLL 16 J=16, D=0 256 12.288 2048 98.304 P=3,R=1, 12.288 PLL 8 12.288 PLL 8 6.144 PLL 16 J=16, D=0 96 kHz 32 3.072 1024 98.304 P=0,R=1, 24.576 PLL 4 24.576 PLL 4 6.144 PLL 16 J=16, D=0 32 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: PCM1861 PCM1863 PCM1865 |
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