PCM1861 datasheet(11/115 Pages) TI

11 / 115 page

PCM1861, PCM1863, PCM1865

www.ti.com

SLAS831C – MARCH 2014 – REVISED AUGUST 2014

6.6 Electrical Characteristics, Primary PGA and ADC AC Performance

all specifications at TA = 25°C, AVDD = 3.3V, DVDD = 3.3V, IOVDD = 3.3V, Master Mode, Single Speed Mode, fS = 48kHz,

system clock = 256×fS, 24-bit data (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0dB PGA Gain, –60dB input signal,

Input Channel Signal to Noise ratio

110

Master Mode. at DIFF Input

Input Channel Signal to Noise ratio

32dB PGA Gain, –92dB input signal,

at 32dB

Master Mode at DIFF Input

0dB PGA Gain, –1dB input signal,

Input Channel THD+N

–85

–93

Master Mode at DIFF Input

32dB PGA Gain, –33dB input signal,

Input Channel THD+N at 32dB

–68

–84

Master Mode at DIFF Input

L channel to R channel separation

0dB PGA Gain, –1dB input signal,

–105

line input

Master Mode

L channel to R channel separation

20dB PGA Gain, –1dB input signal,

–105

mic input

Master Mode

L1 channel to L2 channel separation

0dB PGA Gain, –1dB input signal,

–105

line input

Master Mode

R1 channel to R2 channel

0dB PGA Gain, –1dB input signal,

–105

separation line input

Master Mode

L1 channel to L2 channel separation

20dB PGA Gain, –1dB input signal,

–105

mic input

Master Mode

R1 channel to R2 channel

20dB PGA Gain, –1dB input signal,

–105

separation mic input

Master Mode

–12 to +12dB (1dB STEP) , 20dB

Range of the analog PGA

–12(1)

and 32dB

Accuracy of the PGA + ADC

0.5

Matching between PGA + ADCs

0.05

onchip

Full Scale Voltage Input per input

Single Ended Mode

2.1

VRMS

Full Scale Voltage Input per input

Differential Input Mode

2.1

VRMS

0dB PGA Gain, –60dB input signal,

Input Channel Signal to Noise ratio

106

Master Mode. at SE input

Input Channel Signal to Noise ratio

32dB PGA Gain, –92dB input signal,

at 32dB

Master Mode at SE input

0dB PGA Gain, –1dB input signal,

Input Channel THD+N

Master Mode at SE input

32dB PGA Gain, –33dB input signal,

Input Channel THD+N at 32dB

Master Mode at SE input

PCM1865

Input Impedance per pin

PCM1861/3

Differential Input, 1kHz signal on

CMRR

Common Mode Rejection Ratio

both pins and measure level at

output.

(1)

Specified by design.

Submit Documentation Feedback

Product Folder Links: PCM1861 PCM1863 PCM1865

PCM1861 Datasheet(PDF) 11 Page - Texas Instruments

PCM1861 Datasheet(HTML) 11 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL