PCM1861 datasheet(28/115 Pages) TI

28 / 115 page

PCM1861, PCM1863, PCM1865

SLAS831C – MARCH 2014 – REVISED AUGUST 2014

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8.13.4.1 PCM1861 Clock Configuration and selection

The PCM186x offers both Master and Slave functionality. In master mode, a source master clock (of 256, 384 or

512× the sampling rate) can be sourced from either an external crystal (XI/XO) or on an incoming SCK. (see

External Clock-Source Limits for input rate limitations on SCK sources) The clock from XI and SCK are OR'd

internally, allowing either to be used.

The device can generate the other I2S clocks (BCK and LRCK) in master mode (with dividers set in MD0 and

MD1) or be a clock slave to MCK,BCK and LRCK. In this scenario, the device auto-detects the clock divider ratio.

In master mode, BCK per LRCK is fixed at 64. This allows up to 32 bits per channel.

Selection of the appropriate master/slave and clock ratio between MCK and fS can be done using MD0 and MD1.

Table 7 shows the suggested master clock rates for each of the sample rates supported.

Table 7. External Master Clock Rate versus Sampling Frequency

SAMPLING RATE FREQUENCY

SYSTEM CLOCK FREQUENCY (MHz)

(kHz)

256fS

384fS

512fS

8.0

2.048

3.072

4.096

16.0

4.096

6.144

8.192

32.0

8.1920

12.2880

16.3840

44.1

11.2896

16.9344

22.5792

48.0

12.2880

18.4320

24.5760

64.0

16.3840

24.5760

32.7680

88.2

22.5792

33.8688

45.1584

96.0

24.5760

36.8640

49.1520

176.4

45.1584

192.0

49.1520

For slave mode, BCK per LRCK should be set to 64.

8.13.4.2 Clock Sources (PCM186x Software Programmable Devices)

The PCM186x devices support a wide range of options for generating the clocks required to operate the ADC

section, as well as interface and other control blocks as shown in Figure 29.

The clocks for the PLL require a source reference clock. This clock source can be configured on software

devices as the XTAL, SCK or BCK.

The PCM186x software programmable devices share a similar clock tree for the generation and distribution of

clocks Figure 28.

CLK_MODE (Page.0 0x20) is used to configure the clock configuration. Bits [5:7] configure the OR and MUX for

the incoming MCLK.

sources for the ADC, DSP1 and DSP2. These can mostly be ignored for the most common applications, but are

provided for advanced users.

The CLKDET_EN (Page.0, 0x20) register bit (Auto Clock Detector) is important; the clock detector is mainly

functional for slave modes, and for master modes where the master clock is a 256/384/512× multiple of the

incoming data rate.

NOTE

Non audio related master clock sources can be used with the PCM186x software

programmable devices providing the PLL is programmed manually. CLKDET_EN should

be set to 0.

The result of configurations can be checked by reading registers FS_INFO / CURRENT_BCK_RATIO (Page.0

0x73 and 0x74).

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