PCM1861 datasheet(7/115 Pages) TI

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5 Mic Bias

GPIO 1 / Int A / DMIN

MISO / GPIO 0

MC / SCL

MOSI / SDA 23

MS / AD

MD0

VINR3 / VIN3P 30

VINL3 / VIN4P 29

VINR4 / VIN3M 28

VINL4 / VIN4M 27

1 VINL2 / VIN1M

2 VINR2 / VIN2M

3 VINL1 / VIN1P

4 VINR1 / VIN2P

6 VREF

7 AGND

8 AVDD

15 SCKI (3.3V)

LRCK

DOUT

BCK

GPIO 2 / Int B / DMCLK

GPIO 3 / Int C

LDO

DGND

DVDD

IOVDD

PCM1861, PCM1863, PCM1865

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SLAS831C – MARCH 2014 – REVISED AUGUST 2014

5.2 Pin Assignments, PCM1863, PCM1865

The DMIN2 option for pin 22 is only available on the PCM1865 device.

Figure 2. Device Pin Assignments, PCM1863, PCM1865

Table 2. Pin Descriptions PCM1863, PCM1865

I/O

DESCRIPTIONS

NAME

NO.

VINL2/VIN1M

Analog input 2, L-channel (or Differential M input for input 1)

VINR2/VIN2M

Analog input 2, R-channel (or Differential M input for input 2)

VINL1/VIN1P

Analog input 1, L-channel (or Differential P input for input 1)

VINR1/VIN2P

Analog input 1, R-channel (or Differential P input for input 2)

Mic Bias

–

Mic Bias

VREF

–

Reference voltage decoupling (= 0.5 VCC)

AGND

–

Analog GND

AVDD

–

Analog power supply, +3.3V

–

Oscillation amplifier output (Connect External Crystal if needed here)

Oscillation amplifier input (Connect External Crystal if needed here)

LDO

–

LDO output (or +1.8V input to bypass LDO)

DGND

–

Digital GND

DVDD

–

Digital power supply, +3.3V

IOVDD

–

Power Supply for I/O Voltages (for example, +3.3V or +1.8V)

SCKI

CMOS Level (+3.3V) Master Clock Input

LRCK

I/O

Audio data latch enable input/output(1)

BCK

I/O

Audio data bit clock input/output (1)

DOUT

Audio data digital output

GPIO 3 / INT C

I/O

GPIO 3 or Interrupt C

GPIO2 / INT B / DMCLK

I/O

GPIO 2, Interrupt B or Digital Microphone Clock Output

(1)

Schmitt trigger input with internal pull-down (50k

Ω typically).

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