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PCM1861 Datasheet(PDF) 83 Page - Texas Instruments |
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PCM1861 Datasheet(HTML) 83 Page - Texas Instruments |
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83 / 115 page  PCM1861, PCM1863, PCM1865 www.ti.com SLAS831C – MARCH 2014 – REVISED AUGUST 2014 Default value: 0 0: configured as analog ADC signal processing (Default) 1: configured as digital MIC signal processing Page 0 / Register 27 (Hex 0x1B) Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 27 0x1B RSV RSV 1 0 RSV RSV DIN_RESAMP1 DIN_RESAMP0 Reset Value 0 0 0 0 0 0 0 0 RSV Reserved Reserved. Do not access. DIN_RESAMP[1:0] Resample DIN with internal BCK to avoid internal timing issue Default value: 00 00: No resample (Default) 01: resample DIN with rising edge of BCK 10: resample DIN with falling edge of BCK 11: Not supported Page 0 / Register 32 (Hex 0x20) Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 32 0x20 SCK_XI_SEL1 SCK_XI_SEL0 MST_SCK_SRC MST_MODE ADC_CLK_SRC DSP2_CLK_SRC DSP1_CLK_SRC CLKDET_EN Reset Value 0 0 0 0 0 0 0 1 SCK_XI_SEL[1:0] SCK/Xtal selection SCK/Xtal selection Default value: 00 00: SCK or Xtal (Default) 01: SCK 10: Xtal 11: (Reserved) MST_SCK_SRC Master-Mode SCK source select Default value: 0 0: SCK or XI (Default) 1: BCK MST_MODE Master/Slave selection Default value: 0 0: Slave (Default) 1: Master ADC_CLK_SRC ADC Clock Source selection. Ignored if CLKDET_EN = 1 Default value: 0 0: SCK (Default) 1: PLL DSP2_CLK_SRC DSP2 Clock Source selection. Ignored if CLKDET_EN = 1 Default value: 0 0: SCK (Default) 1: PLL DSP1_CLK_SRC DSP1 Clock Source selection. Ignored if CLKDET_EN = 1 Default value: 0 Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 83 Product Folder Links: PCM1861 PCM1863 PCM1865 |
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