ADSP-SC583 datasheet(5/168 Pages) AD

5 / 168 page

Preliminary Technical Data

Rev. PrF

Page 5 of 168

February 2016

ADSP-SC582/583/584/587/589/ADSP-21583/584/587

ARM CORTEX-A5 PROCESSOR

The ARM Cortex-A5 processor (Figure 2) is a high performance

processor with the following features:

• Instruction and Data L1 cache units (32/32K bytes)

• In-order pipeline with dynamic branch prediction

• ARM, Thumb, and ThumbEE instruction set support

• TrustZone security extensions

• Harvard level 1 memory system with a memory manage-

ment unit (MMU)

•ARM v7 debug architecture

• Trace support through an embedded trace macrocell

(ETM) interface

• Extension: vector floating-point unit (IEEE754) with trap-

less execution

• Extension: media processing engine (MPE) with NEON

technology

• Extension: Jazelle hardware acceleration

Figure 2. ARM Cortex A-5 Processor Block Diagram

DATA STORE

BUFFER (STB)

BUS INTERFACE UNIT (BIU)

PREFETCH UNIT AND BRANCH PREDICTOR (PFU)

DATA PROCESSING UNIT (DPU)

DATA MICRO-TLB

INSTRUCTION MICRO-TLB

DEBUG

DATA CACHE

UNIT (DCU)

MAIN TRANSMISSION

LOOKINSIDE BUFFER (TLB)

INSTRUCTION CACHE

UNIT (ICU)

CORTEX-A5

PROCESSOR

EMBEDDED TRACE MACROCELL

(ETM) INTERFACE

L2 CACHE

CONTROLLER

(CoreLinkTM PL-310)

256 KB

SYSTEM FABRIC

TO OTHER CORES

A5 BUS MASTER PORT

CoreSight INTERFACE

CP15

NEON MEDIA

PROCESSING

ENGINE

32 KB

GENERIC INTERRUPT

CONTROLLER

(PrimeCell® PL-390)

DATA MASTER PORTS

SHARC PROCESSORS

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