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ADSP-SC583 Datasheet(PDF) 30 Page - Analog Devices |
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ADSP-SC583 Datasheet(HTML) 30 Page - Analog Devices |
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30 / 168 page  Rev. PrF | Page 30 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data 349-BALL CSP_BGA SIGNAL DESCRIPTIONS The processor’s pin definitions are shown in Table 12. The col- umns in this table provide the following information: • Signal Name: The Signal Name column in the table includes the signal name for every pin and (where applica- ble) the GPIO multiplexed pin function for every pin. • Description: The Description column in the table provides a verbose (descriptive) name for the signal. • General-Purpose Port: The Port column in the table shows whether or not the signal is multiplexed with other signals on a general-purpose I/O port pin. • Pin Name: The Pin Name column in the table identifies the name of the package pin (at power on reset) on which the signal is located (if a single function pin) or is multiplexed (if a general-purpose I/O pin). Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions Signal Name Description Port Pin Name ACM0_A0 ACM0 ADC Control Signals C PC_13 ACM0_A1 ACM0 ADC Control Signals C PC_14 ACM0_A2 ACM0 ADC Control Signals C PC_15 ACM0_A3 ACM0 ADC Control Signals D PD_00 ACM0_A4 ACM0 ADC Control Signals D PD_01 ACM0_T0 ACM0 External Trigger n C PC_12 C1_FLG0 SHARC Core 1 Flag Pin E PE_01 C1_FLG1 SHARC Core 1 Flag Pin E PE_03 C1_FLG2 SHARC Core 1 Flag Pin E PE_05 C1_FLG3 SHARC Core 1 Flag Pin E PE_07 C2_FLG0 SHARC Core 2 Flag Pin E PE_02 C2_FLG1 SHARC Core 2 Flag Pin E PE_04 C2_FLG2 SHARC Core 2 Flag Pin E PE_06 C2_FLG3 SHARC Core 2 Flag Pin E PE_08 CAN0_RX CAN0 Receive C PC_07 CAN0_TX CAN0 Transmit C PC_08 CAN1_RX CAN1 Receive B PB_10 CAN1_TX CAN1 Transmit B PB_09 CNT0_DG CNT0 Count Down and Gate B PB_14 CNT0_UD CNT0 Count Up and Direction B PB_12 CNT0_ZM CNT0 Count Zero Marker B PB_11 DAI0_PIN01 DAI0 Pin 1 Not Muxed DAI0_PIN01 DAI0_PIN02 DAI0 Pin 2 Not Muxed DAI0_PIN02 DAI0_PIN03 DAI0 Pin 3 Not Muxed DAI0_PIN03 DAI0_PIN04 DAI0 Pin 4 Not Muxed DAI0_PIN04 DAI0_PIN05 DAI0 Pin 5 Not Muxed DAI0_PIN05 DAI0_PIN06 DAI0 Pin 6 Not Muxed DAI0_PIN06 DAI0_PIN07 DAI0 Pin 7 Not Muxed DAI0_PIN07 DAI0_PIN08 DAI0 Pin 8 Not Muxed DAI0_PIN08 DAI0_PIN09 DAI0 Pin 9 Not Muxed DAI0_PIN09 DAI0_PIN10 DAI0 Pin 10 Not Muxed DAI0_PIN10 DAI0_PIN11 DAI0 Pin 11 Not Muxed DAI0_PIN11 DAI0_PIN12 DAI0 Pin 12 Not Muxed DAI0_PIN12 DAI0_PIN19 DAI0 Pin 19 Not Muxed DAI0_PIN19 DAI0_PIN20 DAI0 Pin 20 Not Muxed DAI0_PIN20 DAI1_PIN01 DAI1 Pin 1 Not Muxed DAI1_PIN01 DAI1_PIN02 DAI1 Pin 2 Not Muxed DAI1_PIN02 DAI1_PIN03 DAI1 Pin 3 Not Muxed DAI1_PIN03 |
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