ADSP-SC583 datasheet(21/168 Pages) AD

21 / 168 page

Preliminary Technical Data

Rev. PrF

Page 21 of 168

February 2016

ADSP-SC582/583/584/587/589/ADSP-21583/584/587

From a system perspective reset is defined by both the reset tar-

get and the reset source as described below.

Target defined:

• System reset: All functional units except the RCU are set to

their default states.

• Hardware reset: All functional units are set to their default

states without exception. History is lost.

• Core-only reset: Affects the core only. The system software

should guarantee that the core, while in reset state, is not

accessed by any bus master.

Source defined:

• System reset: May be triggered by software (writing to the

RCU_CTL register) or by another functional unit such as

the dynamic power management (DPM) unit or any of the

system event controllers (SEC), trigger routing unit (TRU),

or emulator inputs.

• Hardware reset: The SYS_HWRST input signal is asserted

active (pulled down).

• Core-only reset: Triggered by software.

• Trigger request (peripheral).

Real-Time Clock (RTC)

The real-time clock (RTC) provides a robust set of digital watch

features, including current time, stopwatch, and alarm. The

RTC is clocked by a 32.768 kHz crystal external to the processor.

Connect RTC pins RTC0_CLKIN and RTC0_XTAL with exter-

nal components as shown in Figure 6.

The RTC peripheral has dedicated power supply pins so that it

can remain powered up and clocked even when the rest of the

processor is in a low power state. The RTC provides several

programmable interrupt options, including interrupt per

second, minute, hour, or day clock ticks, interrupt on program-

mable stopwatch countdown, or interrupt at a programmed

alarm time.

The 32.768 kHz input clock frequency is divided down to a 1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 60-second counter, a 60-minute counter, a

24-hour counter, and a 32,768-day counter. When the alarm

interrupt is enabled, the alarm function generates an interrupt

when the output of the timer matches the programmed value in

the alarm control register. There are two alarms: The first alarm

is for a time of day. The second alarm is for a day and time of

that day.

The stopwatch function counts down from a programmed

value, with one-second resolution. When the stopwatch inter-

rupt is enabled and the counter underflows, an interrupt is

generated.

Clock Generation Unit (CGU)

The ADSP-SC58x/ADSP-2158x processors support two inde-

pendent PLLs. Each PLL is part of a clock generation unit

(CGU). (Refer to Figure 8 on Page 82.) Each CGU can either be

driven externally by the same clock source or each can be driven

by separate sources. This provides flexibility in determining the

internal clocking frequencies for each clock domain.

Frequencies generated by each CGU are derived from a com-

mon multiplier with different divider values available for each

output.

The clock generation unit (CGU) generates all on-chip clocks

and synchronization signals. Multiplication factors are pro-

grammed to define the PLLCLK frequency.

Programmable values divide the PLLCLK frequency to generate

the core clock (CCLK), the system clocks, the DDR1/2/3 clock

(DCLK), and the output clock (OCLK). For more information

on clocking, refer to the Clock Generation Unit (CGU) chapter

of the hardware reference manual.

Writing to the CGU control registers does not affect the behav-

ior of the PLL immediately. Registers are first programmed with

a new value, and the PLL logic executes the changes so that it

transitions smoothly from the current conditions to the new

conditions.

System Crystal Oscillator and USB Crystal Oscillator

The processor can be clocked by an external crystal, (Figure 7) a

sine wave input, or a buffered, shaped clock derived from an

external clock oscillator. If an external clock is used, it should be

a TTL compatible signal and must not be halted, changed, or

operated below the specified frequency during normal opera-

tion. This signal is connected to the SYS_CLKIN pin of the

processor. When an external clock is used, the SYS_XTAL pin

must be left unconnected. Alternatively, because the processor

includes an on-chip oscillator circuit, an external crystal may be

used.

For fundamental frequency operation, use the circuit shown in

Figure 7. A parallel-resonant, fundamental frequency, micro-

processor grade crystal is connected across the SYS_CLKIN and

SYS_XTAL pins. The on-chip resistance between SYS_CLKIN

and the SYS_XTAL pin is in the 500 kΩ range. Further parallel

resistors are typically not recommended.

The two capacitors and the series resistor shown in Figure 7

fine-tune phase and amplitude of the sine frequency. The capac-

itor and resistor values shown in Figure 7 are typical values

only. The capacitor values are dependent upon the load capaci-

tance recommendations of the crystal manufacturer and the

PCB physical layout. The resistor value depends on the drive

Figure 6. External Components for RTC

RTC0_CLKIN

RTC0_XTAL

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS.

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