ADSP-SC583 datasheet(22/168 Pages) AD

22 / 168 page

Rev. PrF

Page 22 of 168

February 2016

ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data

level specified by the crystal manufacturer. The user should ver-

ify the customized values based on careful investigations on

multiple devices over the required temperature range.

A third-overtone crystal can be used for frequencies above

25 MHz. The circuit is then modified to ensure crystal operation

only at the third overtone by adding a tuned inductor circuit as

shown in Figure 7. A design procedure for third-overtone oper-

ation is discussed in detail in application note “Using Third

Overtone Crystals with the ADSP-218x DSP” (EE-168). The

same recommendations may be used for the USB crystal

oscillator.

Clock Distribution Unit (CDU)

The two CGUs each provide outputs which feed a clock distri-

bution unit (CDU). The clock outputs CLKO0-9 are connected

to various targets. For more information, refer to the Clock Dis-

tribution Unit (CDU) chapter of the hardware reference

manual.

Power-Up

XTAL oscillations (SYS_CLKIN) start when power is applied to

the VDD_EXT pins. The rising edge of SYS_HWRST starts on-

chip PLL locking (PLL lock counter). The deassertion should

apply only if all voltage supplies and SYS_CLKIN oscillations

are valid (refer to Power-Up Reset Timing on Page 88).

Clock Out/External Clock

The SYS_CLKOUT output pin has programmable options to

output divided-down versions of the on-chip clocks. By default,

the SYS_CLKOUT pin drives a buffered version of the

SYS_ CLKIN0 input. Refer to the Clock Distribution Unit

(CDU) chapter in the hardware reference manual to change the

default mapping of clocks.

Booting

The processors have several mechanisms for automatically load-

ing internal and external memory after a reset. The boot mode is

defined by the SYS_BMODE input pins dedicated for this pur-

pose. There are two categories of boot modes. In master boot

mode, the processor actively loads data from serial memories. In

slave boot modes, the processors receive data from external host

devices.

The boot modes are shown in Table 9. These modes are imple-

mented by the SYS_BMODE bits of the reset configuration

initiated resets.

In the ADSP-SC58x processors, the ARM Cortex-A5 (core 0)

controls the boot process, including loading all internal and

external memory. Likewise, in the ADSP-2158x processors, the

SHARC+ (core 1) controls the boot function. The option for

secure boot is available on all products.

Thermal Monitoring Unit (TMU)

The thermal monitoring unit provides on-chip temp measure-

ment which is important in applications that require substantial

power consumption. The TMU is integrated into the processor

die and digital infrastructure using an MMR-based system

access to measure the die temperature variations in real-time.

TMU features include:

• On-chip temperature sensing

• Programmable over-temperature and under-temperature

limits

• Programmable conversion rate

• Programmable clock source selection to run the sensor off

an independent local clock

• Averaging feature available

Power Supplies

The processors have separate power supply connections for:

• Internal (VDD_INT)

•External (VDD_EXT)

•USB (VDD_USB)

•HADC (VDD_HADC)

Figure 7. External Crystal Connection

SYS_CLKIN

TO PLL

CIRCUITRY

FOR OVERTONE

OPERATION ONLY:

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING

ON THE CRYSTAL AND LAYOUT. ANALYZE CAREFULLY. FOR

FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE

OF 18pF SHOULD BE TREATED AS A MAXIMUM.

18 pF*

SHARC PROCESSOR

SYS_XTAL

Table 9. Boot Modes

SYS_BMODE Setting

Boot Mode

000

No boot

001

SPI2 Master

010

SPI2 Slave

011

Reserved

100

Reserved

101

Reserved

110

Link0 Slave

111

UART0 Slave

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