ADSP-SC583 datasheet(1/168 Pages) AD

Part #	ADSP-SC583

Description	SHARC plus Dual Core DSP with ARM Cortex-A5

PDF	168 Pages

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Manufacturer	AD [Analog Devices]

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Preliminary Technical Data

SHARC+ Dual Core

DSP with ARM Cortex-A5

ADSP-SC582/583/584/587/589/ADSP-21583/584/587

Rev. PrF

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SYSTEM FEATURES

Dual enhanced SHARC+ high performance floating-point

cores

Up to 450 MHz per SHARC+ core

Up to 5 Mbits (640 kB) L1SRAM memory per core with

parity (optional ability to configure as cache)

32-bit, 40-bit, and 64-bit floating-point support

32-bit fixed point

Byte, short-word, word, long-word addressed

ARM Cortex-A5 core

450 MHz/720 DMIPS with Neon/VFPv4-D16/Jazelle

32 kB L1 instruction cache/32 kB L1 data cache

256 kB L2 cache with parity

Powerful DMA system

On-chip memory protection

Integrated safety features

19 mm × 19 mm 349/529 BGA (0.8 pitch), RoHS compliant

Low system power across automotive temperature range

MEMORY

Large on-chip L2 SRAM with ECC protection, up to 256 kB

On-chip L2 ROM (512 kB)

Two L3 interfaces optimized for low system power, providing

16-bit interface to DDR3, DDR2 or LPDDR1 SDRAM devices

ADDITIONAL FEATURES

Security and Protection

Crypto hardware accelerators

Fast secure boot with IP protection

Support for TrustZone®

Accelerators

High performance pipelined FFT/IFFT engine

FIR, IIR, HAE, SINC offload engines

Figure 1. Processor Block Diagram

SYSTEM CONTROL

FAULT MANAGEMENT

SYSTEM PROTECTION (SPU)

SECURITY AND PROTECTION

ARM® TrustZone® SECURITY

DUAL CRC

WATCHDOGS

THERMAL SENSOR

OTP MEMORY

TRIGGER ROUTING (TRU)

SYS EVENT CONTROLLER (SEC)

PROGRAM FLOW

REAL TIME CLOCK (RTC)

CLOCK GENERATION (CGU)

CLOCK, RESET, AND POWER

POWER MANAGEMENT (DPM)

RESET CONTROL (RCU)

WATCHPOINTS (SWU)

ARM® CoreSightTM

DEBUG UNIT

SYSTEM MEMORY

PROTECTION UNIT (SMPU)

CLOCK DISTRIBUTION

UNIT (CDU)

DATA

16

S

L1 SRAM (PARITY)

5M BITS (640 kB)

SRAM/CACHE

32 kB L1 I-CACHE

32 kB L1 D-CACHE

2M BITS (256 kB)

L2 SRAM (ECC)

SYSTEM

L2 MEMORY

SYSTEM

ACCELERATION

L3 MEMORY

INTERFACES

DDR3

DDR2

LPDDR1

DDR3

DDR2

LPDDR1

4M BITS (512 kB)

2 × 2M BITS ROM

DSP FUNCTIONS

(FFT/iFFT, FIR, IIR, HAE/SINC)

L1 SRAM (PARITY)

5M BITS (640 kB)

SRAM/CACHE

ENCRYPTION/DECRYPTION

L1 CACHE

L2 CACHE

256 kB (PARITY)

DATA

16

SYSTEM CROSSBAR AND DMA SUBSYSTEM

CORE 1

CORE 2

CORE 0

S

PERIPHERALS

3× I

2C

2× LINK PORTS

2× SPI + 1× QUAD SPI

3× UARTs

3× ePWM

8× TIMERS + 1× COUNTER

1× EPPI

ADC CONTROL MODULE

(ACM)

ASYNC MEMORY (16-BIT)

SD/SDIO/eMMC

MLB 3-PIN

2× CAN2.0

2× USB 2.0 HS

MLB 6-PIN

PCIe2.0 (1 lane)

HADC (8 CHAN, 12-BIT)

2× EMAC

SINC FILTER

8x SHARC FLAGS

ASRC

8× PAIRS

2× S/PDIF Rx/Tx

4× PRECISION CLOCK

GENERATORS

FULL SPORT

0-7

2x DAI

2x PIN

BUFFER

SRU

G

P

I

O

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