ADSP-SC583 datasheet(19/168 Pages) AD

19 / 168 page

Preliminary Technical Data

Rev. PrF

Page 19 of 168

February 2016

ADSP-SC582/583/584/587/589/ADSP-21583/584/587

• Adaptable conversion type: allows single or continuous

conversion with option of autoscan

• Auto sequencing capability with up to 15 autoconversions

in a single session. Each conversion can be programmed to

select any 1–15 input channels.

• 16 data registers (individually addressable) to store conver-

sion values

USB 2.0 On-the-Go Dual-Role Device Controller

There are two USB modules + PHY. USB0 supports HS/FS/LS

USB2.0 OTG and USB1 supports HS/FS USB2.0 only and can be

programmed to be a host or device.

Each USB 2.0 OTG dual-role device controller provides a low-

cost connectivity solution for the growing adoption of this bus

standard in industrial applications, as well as consumer mobile

devices such as cell phones, digital still cameras, and MP3

players. The USB 2.0 controller allows these devices to transfer

data using a point-to-point USB connection without the need

for a PC host. The module can operate in a traditional USB

peripheral-only mode as well as the host mode presented in the

on-the-go (OTG) supplement to the USB 2.0 specification.

The USB clock is provided through a dedicated external crystal

or crystal oscillator.

The USB on-the-go dual-role device controller includes a phase

locked loop with programmable multipliers to generate the nec-

essary internal clocking frequency for USB.

Media Local Bus (MLB)

The automotive model has a MLB slave interface which allows

the processors to function as a media local bus device. It

includes support for both 3-pin and 6-pin media local bus pro-

tocols. MLB 3-pin supports speeds up to 1024 × FS and 6-pin up

to 4096 × FS (48 kHz). MLB also supports up to 63 logical chan-

nels, with up to 124 bytes of data per media local bus frame.

The MLB interface supports MOST25/50/150 data rates and

operates in slave mode only.

2-Wire Controller Interface (TWI)

The processors include three 2-wire interface (TWI) modules

for providing a simple exchange method of control data

between multiple devices. The TWI module is compatible with

the widely used I2C bus standard. The TWI module offers the

capabilities of simultaneous master and slave operation and

support for both 7-bit addressing and multimedia data arbitra-

tion. The TWI interface utilizes two pins for transferring clock

(TWI_SCL) and data (TWI_SDA) and supports the protocol at

speeds up to 400k bits/sec. The TWI interface pins are compati-

ble with 5 V logic levels.

Additionally, the TWI module is fully compatible with serial

camera control bus (SCCB) functionality for easier control of

various CMOS camera sensor devices.

General-Purpose I/O (GPIO)

Each general-purpose port pin can be individually controlled by

manipulation of the port control, status, and interrupt registers:

• GPIO direction control register: Specifies the direction of

each individual GPIO pin as input or output.

• GPIO control and status registers: A “write one to modify”

mechanism allows any combination of individual GPIO

pins to be modified in a single instruction, without affect-

ing the level of any other GPIO pins.

• GPIO interrupt mask registers: Allow each individual

GPIO pin to function as an interrupt to the processors.

GPIO pins defined as inputs can be configured to generate

hardware interrupts, while output pins can be triggered by

software interrupts.

• GPIO interrupt sensitivity registers: Specify whether indi-

vidual pins are level- or edge-sensitive and specify—if

edge-sensitive—whether just the rising edge or both the ris-

ing and falling edges of the signal are significant.

Pin Interrupts

Every port pin on the processors can request interrupts in either

an edge-sensitive or a level-sensitive manner with programma-

ble polarity. Interrupt functionality is decoupled from GPIO

operation. Six system-level interrupt channels (PINT0–5) are

reserved for this purpose. Each of these interrupt channels can

manage up to 32 interrupt pins. The assignment from pin to

interrupt is not performed on a pin-by-pin basis. Rather, groups

of eight pins (half ports) can be flexibly assigned to interrupt

channels.

Every pin interrupt channel features a special set of 32-bit mem-

ory-mapped registers that enable half-port assignment and

interrupt management. This includes masking, identification,

and clearing of requests. These registers also enable access to the

respective pin states and use of the interrupt latches, regardless

of whether the interrupt is masked or not. Most control registers

feature multiple MMR address entries to write-one-to-set or

write-one-to-clear them individually.

Mobile Storage Interface (MSI)

The mobile storage interface (MSI) controller acts as the host

interface for multimedia cards (MMC), secure digital memory

cards (SD), and secure digital input/output cards (SDIO). The

MSI controller has the following features:

• Support for a single MMC, SD memory, SDIO card

• Support for 1-bit and 4-bit SD modes

• Support for 1-bit, 4-bit, and 8-bit MMC modes

• Support for eMMC 4.3 embedded NAND flash devices

• An 11-signal external interface with clock, command,

optional interrupt, and up to 8 data lines

• Integrated DMA controller

• Card interface clock generation from CLKO9 from CDU

• SDIO interrupt and read wait features

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