ADSP-SC583 datasheet(13/168 Pages) AD

13 / 168 page

Preliminary Technical Data

Rev. PrF

Page 13 of 168

February 2016

ADSP-SC582/583/584/587/589/ADSP-21583/584/587

Memory DMA (MDMA)

The processor supports various memory-to-memory DMA

operations which include:

• Standard bandwidth MDMA channels with CRC protec-

tion (32-bit bus width, run on SCLK0)

• Enhanced bandwidth MDMA channel (32-bit bus width,

runs on SYSCLK)

• Maximum bandwidth MDMA channels (64-bit bus width,

run on SYCLK, one channel may be assigned to the FFT

accelerator)

Extended Memory DMA

Extended memory DMA supports various operating modes

such as delay line (allows processor reads and writes to external

delay line buffers and hence to external memory) with limited

core interaction and scatter/gather DMA (writes to/from non-

contiguous memory blocks).

CRC Protection

The CRC protection modules allow system software to calculate

the signature of code or data or both in memory, the content of

memory-mapped registers, or communication message objects

periodically. Dedicated hardware circuitry compares the signa-

ture with pre calculated values and triggers appropriate fault

events.

For example, every 100 ms the system software initiates the sig-

nature calculation of the entire memory contents and compares

these contents with expected, pre calculated values. If a mis-

match occurs, a fault condition is generated (through the

processor core or the trigger routing unit).

The CRC is a hardware module based on a CRC32 engine that

computes the CRC value of the 32-bit data words presented to

it. The source channel of the memory-to-memory DMA (in

memory scan mode) provides data. The data forwards option-

ally to the destination channel (memory transfer mode). The

main features of the CRC peripheral are:

•Memory scan mode

• Memory transfer mode

•Data verify mode

• Data fill mode

• User-programmable CRC32 polynomial

• Bit/byte mirroring option (endianness)

• Fault/error interrupt mechanisms

• 1D and 2D fill block to initialize array with constants

• 32-bit CRC signature of a block of a memory or MMR

block

Event Handling

The processors provide event handling that supports both nest-

ing and prioritization. Nesting allows multiple event service

routines to be active simultaneously. Prioritization ensures that

servicing of a higher-priority event takes precedence over ser-

vicing of a lower-priority event. The processors provide support

for five different types of events:

• Emulation: An emulation event causes the processors to

enter emulation mode, allowing command and control of

the processors through the JTAG interface.

• Reset: This event resets the processors.

• Exceptions: Events that occur synchronously to program

flow (in other words, the exception is taken before the

instruction is allowed to complete). Conditions triggered

on the one side by the SHARC+ core, such as data align-

ment (SIMD/long word) or compute violations (fixed or

floating point), and illegal instructions cause core excep-

tions. Conditions triggered on the other side by the SEC,

such as ECC/parity/watchdog/system clock, cause system

exceptions.

• Interrupts: Events that occur asynchronously to program

flow. They are caused by input signals, timers, and other

peripherals, as well as by an explicit software instruction.

System Event Controller (SEC)

Both SHARC+ cores feature a system event controller. System

event controller features include the following:

• Comprehensive system event source management includ-

ing interrupt enable, fault enable, priority, core mapping

and source grouping

• Distributed programming model where each system event

source control and all status fields are independent of all

others

• Determinism where all system events have the same propa-

gation delay and provide unique identification of a specific

system event source

• Slave Control Port which provides access to all SEC regis-

ters for configuration, status, and interrupt/fault service

model

• Global locking supports a register level protection model to

prevent writes to “locked” registers

• Fault management including fault action configuration,

time out, external indication, and system reset

Trigger Routing Unit (TRU)

The TRU provides system-level sequence control without core

intervention. The TRU maps trigger masters (generators of trig-

gers) to trigger slaves (receivers of triggers). Slave endpoints can

be configured to respond to triggers in various ways. Common

applications enabled by the TRU include:

• Automatically triggering the start of a DMA sequence after

a sequence from another DMA channel completes

• Software triggering

• Synchronization of concurrent activities

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