ADSP-SC583 datasheet(9/168 Pages) AD

9 / 168 page

Preliminary Technical Data

Rev. PrF

Page 9 of 168

February 2016

ADSP-SC582/583/584/587/589/ADSP-21583/584/587

processing elements, but each processing element operates on

different data. This architecture is efficient at executing math-

intensive DSP algorithms. In addition to all the features of its

predecessors, the SHARC+ core also provides a new and sim-

pler way to execute an instruction only on PEy.

SIMD mode also affects the way data transfers between memory

and the processing elements because to sustain computational

operation in the processing elements requires twice the data

bandwidth. Therefore, entering SIMD mode also doubles the

bandwidth between memory and the processing elements.

When using the DAGs to transfer data in SIMD mode, two data

values transfer with each memory or register file access.

Independent, Parallel Computation Units

Within each processing element is a set of pipelined computa-

tional units. The computational units consist of an

arithmetic/logic unit (ALU), multiplier, and shifter. These units

are arranged in parallel, maximizing computational throughput.

These computational units support IEEE 32-bit single-precision

floating-point, 40-bit extended-precision floating-point, IEEE

64-bit double-precision floating-point, and 32-bit fixed-point

data formats.

Multifunction instruction set supports parallel execution of

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing ele-

ments per core.

All processing operations take one cycle to complete. For all

floating-point operations, the processor takes two cycles to

complete in case of data dependency. Double-precision float-

ing-point data take two to six cycles to complete. The processor

stalls for the appropriate number of cycles (interlocked pipeline

plus data dependency check).

Core Timer

Each SHARC+ processor core also has its own dedicated timer.

This extra timer is clocked by the internal processor clock and is

typically used as a system tick clock for generating periodic

operating system interrupts.

Data Register File

Each processing element contains a general-purpose data regis-

ter file. The register files transfer data between the computation

units and the data buses, and store intermediate results. These

10-port, 32-register (16 primary, 16 secondary) register files,

combined with the enhanced Harvard architecture of the pro-

cessor, allow unconstrained data flow between computation

units and internal memory. The registers in PEx are referred to

as R0-R15 and in PEy as S0-S15.

Context Switch

Many of the registers of the processor have secondary registers

that can activate during interrupt servicing for a fast context

switch. The data registers in the register file, the DAG registers,

and the multiplier result registers all have secondary registers.

The primary registers are active at reset, while control bits in a

mode control register activate the secondary registers.

Universal Registers

General-purpose tasks use these registers. The USTAT (4) regis-

ters allow easy bit manipulations (Set, Clear, Toggle, Test, XOR)

for all peripheral registers (control/status).

The data bus exchange register (PX) permits data to pass

between the 64-bit PM data bus and the 64-bit DM data bus, or

between the 40-bit register file and the PM/DM data bus. These

registers contain hardware to handle the data width difference.

Data Address Generators With Zero-Overhead Hardware

Circular Buffer Support

For indirect addressing and implementing circular data buffers

in hardware, the processor uses the two data address generators

(DAGs). Circular buffers allow efficient programming of delay

lines and other data structures required in digital signal process-

ing, and are commonly used in digital filters and Fourier

transforms. The two DAGs of the processors contain sufficient

registers to allow the creation of up to 32 circular buffers (16

primary register sets, 16 secondary). The DAGs automatically

handle address pointer wraparound, reduce overhead, increase

performance, and simplify implementation. Circular buffers can

start and end at any memory location.

Flexible ISA Instruction Set

The 48-bit instruction word accommodates various parallel

operations for concise programming. For example, the

processors can conditionally execute a multiply, an add, and a

subtract in both processing elements while branching and fetch-

ing up to four 32-bit values from memory—all in a single

instruction. Additionally, the double precision floating-point

instruction set is an addition to the SHARC+ core.

Variable Instruction Set Architecture (VISA)

In addition to supporting the standard 48-bit instructions (ISA)

from previous SHARC processors, the SHARC+ core processors

support new instructions of 16 and 32 bits for ADSP-214xx

products. This feature, called Variable Instruction Set Architec-

ture (VISA), drops redundant/unused bits within the 48-bit

instruction to create more efficient and compact code. The pro-

gram sequencer supports fetching these 16-bit and 32-bit

instructions from both internal and external memories. VISA is

not an operating mode, it is only address-dependent (refer to

memory map ISA/VISA address spaces). Furthermore, it allows

jumps between ISA and VISA instruction fetches.

Single-Cycle Fetch of Instructional Four Operands

The ADSP-SC58x/ADSP-2158x processors feature an enhanced

Harvard architecture in which the data memory (DM) bus

transfers data and the program memory (PM) bus transfers

both instructions and data.

With its separate program and data memory buses and on-chip

instruction conflict-cache, the processors can simultaneously

fetch four operands (two over each data bus) and one instruc-

tion (from the conflict-cache), all in a single cycle.

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