ADSP-SC583 datasheet(8/168 Pages) AD

8 / 168 page

Rev. PrF

Page 8 of 168

February 2016

ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data

The memory map in Table 4 on Page 11 gives the L1 memory

address space.

In addition, there are multiple L1 memory blocks offering a

configurable mix of SRAM and cache.

L1 Master and Slave Ports

Each SHARC+ core has two master and two slave ports to/from

the system fabric. One master port fetches instructions; the sec-

ond master port drives data to the system world. Both slave

ports allow conflict free core/DMA streams to the individual

memory blocks. For slave port addresses, refer to the L1 mem-

ory address map.

L1 On-Chip Memory Bandwidth

The internal memory architecture allows programs to have four

accesses at the same time to any of the four blocks (assuming no

block conflicts). The total bandwidth is realized using the DMD

and PMD buses (2 × 64-bits, CCLK speed and 2 × 32-bit,

SYSCLK speed).

Instruction and Data Cache

The ADSP-SC58x/ADSP-2158x processors also include a tradi-

tional instruction cache (I-cache) and two data caches. (PM/DM

caches). Together, these caches support one instruction access

and two data accesses, over the DM and PM buses, per cycle.

The cache controllers automatically manage the configured part

of the L1 memory. The system can configure part of the L1

memory for automatic management by the cache controllers.

The sizes of these caches are independently configurable from

zero to a maximum of 128 kB each. The memory not managed

by the cache controllers is directly addressable by the proces-

sors. The controllers ensure the data coherence between the two

data caches. The caches provide user-controllable features such

as locking (full as well as partial), range-bound invalidation, and

flushing.

System Event Controller Input

The output of the SEC controller is forwarded to the core event

controller (CEC) to respond directly to all unmasked system

based interrupts. It also supports nesting including various SEC

interrupt channel arbitration options. For all SEC channels the

processor automatically stacks the arithmetic status (ASTATx,

and STATy) registers and mode (MODE1) registers in parallel

with the interrupt servicing.

Core Memory-Mapped Registers (CMMR)

The core memory mapped registers control L1 I/D cache, BTB,

L2 cache, parity error, system control, debug and monitor

functions.

SHARC+ CORE ARCHITECTURE

The ADSP-SC58x/ADSP-2158x processors are code compatible

at the assembly level with the ADSP-2148x, ADSP-2147x,

ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x,

ADSP-21160, and ADSP-21161, and with the first generation

ADSP-2106x SHARC processors. The ADSP-SC58x/ADSP-

2158x processors share architectural features with the

ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-214xx and

ADSP-2116x SIMD SHARC processors, as shown in Figure 4

and detailed in the following sections.

SIMD Computational Engine

The SHARC+ core contains two computational processing ele-

ments that operate as a single-instruction, multiple-data

(SIMD) engine. The processing elements are referred to as PEx

and PEy and each contains an ALU, multiplier, shifter, and reg-

ister file. PEx is always active, and PEy is enabled by setting the

PEYEN mode bit in the MODE1 register. SIMD mode allows

the processors to execute the same instruction in both

Figure 5. ADSP-SC58x/ADSP-2158x Memory Map

0x FFFF FFFF

0x C000 0000

0x 8000 0000

0x 6000 0000

0x 5000 0000

0x 4C00 0000

0x 4800 0000

0x 4400 0000

0x 4000 0000

0x 3000 0000

0x 28FA 0000

0x 28A4 0000

0x 287A 0000

0x 2824 0000

0x 202B FFFF

0x 201B FFFF

0x 2028 0000

0x 2020 7FFF

0x 2020 0000

0x 2018 0000

0x 2010 7FFF

0x 2010 0000

0x 200B FFFF

0x 2008 0000

0x 2000 7FFF

DMC1 (1GB)

DMC0 (1GB)

SPI2 FLASH (512MB)

PCIe DATA (256MB)

SMC BANK 3 (64MB)

SMC BANK 2 (64MB)

SMC BANK 1 (64MB)

SMC BANK 0 (64MB)

SYSTEM MMR SPACE

RESERVED

SHARC2 LI MEMORY IN

MULTIPROCESSOR SPACE

RESERVED

SHARC1 LI MEMORY IN

MULTIPROCESSOR SPACE

RESERVED

L2 ROM 2 (2Mb)

RESERVED

L2 BOOT ROM 2 (0.25Mb)

(SHARC Cores)

RESERVED

L2 ROM 1 (2Mb)

RESERVED

L2 SRAM (2Mb)

RESERVED

L2 BOOT ROM 0 (0.25Mb)

(ARM CORE 0)

L2 BOOT ROM 1 (0.25Mb)

(SHARC Cores)

0x 2000 0000

0x 0039 FFFF

0x 0038 0000

0x 0031 FFFF

0x 0030 0000

0x 002E FFFF

0x 002C 0000

0x 0026 FFFF

0x 0024 0000

0x 0000 0000

RESERVED

L1 BLOCK 3 SRAM (1Mb)

RESERVED

L1 BLOCK 2 SRAM (1Mb)

L1 BLOCK 1 SRAM (1.5Mb)

L1 BLOCK 0 SRAM (1.5Mb)

RESERVED/CORE MMRs/

OTHER MEMORY ALIASES

RESERVED

ARM L2 CONFIG REGS (4KB)

RESERVED

ARM BOOT (32KB)

0x 2000 0000

0x 1000 1000

0x 1000 0000

0x 0000 7FFF

0x 0000 0000

UNIFIED

ADDRESS

SPACE

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