ADSP-SC583 datasheet(18/168 Pages) AD

18 / 168 page

Rev. PrF

Page 18 of 168

February 2016

ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data

Controller Area Network (CAN)

There are two CAN modules. A CAN controller implements the

CAN 2.0B (active) protocol. This protocol is an asynchronous

communications protocol used in both industrial and automo-

tive control systems. The CAN protocol is well suited for

control applications due to its capability to communicate

reliably over a network. This is because the protocol incorpo-

rates CRC checking, message error tracking, and fault node

confinement.

The CAN controller offers the following features:

• 32 mailboxes (8 receive only, 8 transmit only, 16 configu-

rable for receive or transmit)

• Dedicated acceptance masks for each mailbox

• Additional data filtering on first two bytes

• Support for both the standard (11-bit) and extended (29-

bit) identifier (ID) message formats

• Support for remote frames

• Active or passive network support

• Interrupts, including: TX complete, RX complete, error

and global

An additional crystal is not required to supply the CAN clock, as

the CAN clock is derived from a system clock through a pro-

grammable divider.

Timers

The processors include several timers which are described in the

following sections.

General-Purpose Timers (TIMER)

There is one GP timer unit, and it provides eight general-pur-

pose programmable timers. Each timer has an external pin that

can be configured either as a pulse width modulator (PWM) or

timer output, as an input to clock the timer, or as a mechanism

for measuring pulse widths and periods of external events.

These timers can be synchronized to an external clock input on

the TIMER_TMRx pins, an external TIMER_CLK input pin, or

to the internal SCLK0.

These timer units can be used in conjunction with the UARTs

and the CAN controller to measure the width of the pulses in

the data stream to provide a software auto-baud detect function

for the respective serial channels.

The GP timers can generate interrupts to the processor core,

providing periodic events for synchronization to either the sys-

tem clock or to external signals. Timer events can also trigger

other peripherals via the TRU (for instance, to signal a fault).

Each timer may also be started and/or stopped by any TRU

master without core intervention.

Watchdog Timer (WDT)

Two on-chip software watchdog timers can be used by the ARM

and/or SHARC+ cores. A software watchdog can improve sys-

tem availability by forcing the processors to a known state, via a

general-purpose interrupt, or a fault, if the timer expires before

being reset by software. The programmer initializes the count

value of the timer, enables the appropriate interrupt, then

enables the timer. Thereafter, the software must reload the

counter before it counts down to zero from the programmed

value. This protects the system from remaining in an unknown

state where software that would normally reset the timer has

stopped running due to an external noise condition or software

error.

General-Purpose Counters (CNT)

A 32-bit counter is provided that can operate in general-pur-

pose up/down count modes and can sense 2-bit quadrature or

binary codes as typically emitted by industrial drives or manual

thumbwheels. Count direction is either controlled by a level-

sensitive input pin or by two edge detectors.

A third counter input can provide flexible zero marker support

and can alternatively be used to input the push-button signal of

thumbwheel devices. All three pins have a programmable

debouncing circuit.

Internal signals forwarded to a GP timer enable this timer to

measure the intervals between count events. Boundary registers

enable auto-zero operation or simple system warning by inter-

rupts when programmed count values are exceeded.

PCI Express (PCIe)

A PCI express interface is available on some product variants.

This single, bidirectional lane can be configured to be either a

root complex (RC) or end point (EP) system. The interface has

the following features:

• Compliance with the PCI Express Base Specification 3.0

• Support for transfers at either 2.5 Gbps (Gen 1.1) or

5.0 Gbps (Gen 2) in each direction

• Support for 8b/10b encode and decode

• Lane reversal and lane polarity inversion

• Flow control of data in both the transmit and receive

directions

• Support for removal of corrupted packets for error detec-

tion and recovery

• Maximum transaction payload of 256 bytes

Housekeeping Analog-to-Digital Converter (HADC)

The HADC provides a general-purpose, multi-channel succes-

sive approximation A-to-D converter. It supports the following

set of features:

• 12-bit ADC core (10-bit accuracy) with built in sample and

hold

• 8 single-ended input channels that can be extended to 15

channels by adding an external channel multiplexer

• Throughput rates up to 1 MSPS

• Single external reference with analog inputs between 0 and

3.3 V

• Selectable ADC clock frequency including the ability to

program a pre-scaler

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