ADSP-SC583 datasheet(16/168 Pages) AD

16 / 168 page

Rev. PrF

Page 16 of 168

February 2016

ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data

The S/PDIF receiver/transmitter has no separate DMA chan-

nels. It receives audio data in serial format and converts it into a

biphase encoded signal. The serial data input to the

receiver/transmitter can be formatted as left-justified, I2S or

right-justified with word widths of 16, 18, 20, or 24 bits. The

serial data, clock, and frame sync inputs to the S/PDIF

receiver/transmitter are routed through the signal routing unit

(SRU). They can come from a variety of sources, such as the

SPORTs, external pins, and the precision clock generators

(PCGs), and are controlled by the SRU control registers.

Precision Clock Generators (PCG)

The precision clock generators (PCG) consist of four units,

units A/B located in DAI0 and units C/D located into DAI1.

The PCG can generate a pair of signals (clock and frame sync)

derived from a clock input signal (CLKIN1-0, SCLK0, DAI pin

buffer). Each unit can also access the opposite DAI unit. All

units are identical in functionality and operate independently of

each other. The two signals generated by each unit are normally

used as a serial bit clock/frame sync pair.

Parallel Peripheral Interface (PPI)

The processors provide a parallel peripheral interface (PPI) that

supports data widths up to 24 bits. The PPI supports direct con-

nection to TFT LCD panels, parallel analog-to-digital and

digital-to-analog converters, video encoders and decoders,

image sensor modules and other general-purpose peripherals.

The following features are supported in the PPI module:

• Programmable data length: 8 bits, 10 bits, 12 bits, 14 bits,

16 bits, 18 bits and 24 bits per clock

• Various framed, non-framed, and general-purpose operat-

ing modes. Frame syncs can be generated internally or can

be supplied by an external device.

• ITU-656 status word error detection and correction for

ITU-656 receive modes and ITU-656 preamble and status

word decode

• Optional packing and unpacking of data to/from 32 bits

from/to 8 bits, 16 bits and 24 bits. If packing/unpacking is

enabled, endianness can be configured to change the order

of packing/unpacking of bytes/words.

• RGB888 can be converted to RGB666 or RGB565 for trans-

mit modes.

• Various de-interleaving/interleaving modes for receiv-

ing/transmitting 4:2:2 YCrCb data

• Configurable LCD data enable (DEN) output available on

Frame Sync 3

UART Ports

The processors provide three full-duplex universal asynchro-

nous receiver/transmitter (UART) ports, which are fully

compatible with PC-standard UARTs. Each UART port pro-

vides a simplified UART interface to other peripherals or hosts,

supporting full-duplex, DMA-supported, asynchronous

transfers of serial data. A UART port includes support for five to

eight data bits, and none, even, or odd parity. Optionally, an

additional address bit can be transferred to interrupt only

addressed nodes in multi-drop bus (MDB) systems. A frame is

terminated by a configurable number of stop bits.

The UART ports support automatic hardware flow control

through the clear-to-send (CTS) input and request-to-send

(RTS) output with programmable assertion FIFO levels.

To help support the Local Interconnect Network (LIN) proto-

cols, a special command causes the transmitter to queue a break

command of programmable bit length into the transmit buffer.

Similarly, the number of stop bits can be extended by a pro-

grammable inter-frame space.

Serial Peripheral Interface (SPI) Ports

The processors have three industry-standard SPI-compatible

ports that allow it to communicate with multiple SPI-compati-

ble devices.

The baseline SPI peripheral is a synchronous, four-wire inter-

face consisting of two data pins, one device select pin, and a

gated clock pin. The two data pins allow full-duplex operation

to other SPI-compatible devices. An additional two (optional)

data pins are provided to support quad SPI operation. Enhanced

modes of operation such as flow control, fast mode and dual-

I/O mode (DIOM) are also supported. In addition, a direct

memory access (DMA) mode allows for transferring several

words with minimal CPU interaction.

With a range of configurable options, the SPI ports provide a

glueless hardware interface with other SPI-compatible devices

in master mode, slave mode, and multimaster environments.

The SPI peripheral includes programmable baud rates, clock

phase, and clock polarity. The peripheral can operate in a multi-

master environment by interfacing with several other devices,

acting as either a master device or a slave device. In a multimas-

ter environment, the SPI peripheral uses open-drain outputs to

avoid data bus contention. The flow control features enable slow

slave devices to interface with fast master devices by providing

an SPI Ready pin which flexibly controls the transfers.

The SPI port’s baud rate and clock phase/polarities are pro-

grammable, and it has integrated DMA channels for both

transmit and receive data streams.

Link Ports (LP)

Two 8-bit wide link ports can connect to the link ports of other

DSPs or peripherals. Link ports are bidirectional ports having

eight data lines, an acknowledge line, and a clock line.

ADC Control Module (ACM) Interface

The ADC control module (ACM) provides an interface that

synchronizes the controls between the processors and an ana-

log-to-digital converter (ADC). The analog-to-digital

conversions are initiated by the processors, based on external or

internal events.

The ACM allows for flexible scheduling of sampling instants

and provides precise sampling signals to the ADC.

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