DP83932C datasheet(40/98 Pages) NSC

40 / 98 page

40 SONIC Registers (Continued)

438 Transmit Registers

The transmit registers described in this section are part of

the User Register set The UTDA and CTDA must be initial-

ized prior to issuing the transmit command (setting the TXP

bit) in the Command register

Upper Transmit Descriptor Address Register (UTDA)

This register contains the upper address bits (Ak3116l)

for accessing the transmit descriptor area (TDA) and is con-

catenated with the contents of the CTDA when the SONIC

accesses the TDA in system memory The TDA can be as

large as 32k words or 16k long words and can be located

anywhere in system memory This register is unaffected by

a hardware or software reset

Current Transmit Descriptor Address Register (CTDA)

The 16-bit CTDA register contains the lower address bits

(Ak151l) of the 32-bit transmit descriptor address During

initialization this register must be programmed with the low-

er address bits of the transmit descriptor The SONIC con-

catenates the contents of this register with the contents of

the UTDA to point to the transmit descriptor For 32-bit

memory systems bit 1 corresponding to address signal A1

must be set to ‘‘0’’ for alignment to long-word boundaries

Bit 0 of this register is the End of List (EOL) bit and is used

to denote the end of the list This register is unaffected by a

hardware or software reset

439 Receive Registers

The receive registers described in this section are part of

the User Register set A software reset has no effect on

these registers and a hardware reset only affects the EOBC

and RSC registers The receive registers must be initialized

prior to issuing the receive command (setting the RXEN bit)

in the Command register

Upper Receive Descriptor Address Register (URDA)

This register contains the upper address bits (Ak3116l)

for accessing the receive descriptor area (RDA) and is con-

catenated with the contents of the CRDA when the SONIC

accesses the RDA in system memory The RDA can be as

large as 32k words or 16k long words and can be located

anywhere in system memory This register is unaffected by

a hardware or software reset

Current Receive Descriptor Address Register (CRDA)

The CRDA is a 16-bit readwrite register used to locate the

received packet descriptor block within the RDA It contains

the lower address bits (Ak151l) The SONIC concate-

nates the contents of the CRDA with the contents of the

URDA to form the complete 32-bit address The resulting

32-bit address points to the first field of the descriptor block

For 32-bit memory systems bit 1 corresponding to address

signal A1 must be set to ‘‘0’’ for alignment to long-word

boundaries Bit 0 of this register is the End of List (EOL) bit

and is used to denote the end of the list This register is

unaffected by a hardware or software reset

End of Buffer Word Count Register (EOBC)

The SONIC

uses the contents of this register to determine where to

place the next packet At the end of packet reception the

SONIC compares the contents of the EOBC register with

the contents of the Remaining Buffer Word Count registers

(RBWC01) to determine whether (1) to place the next

packet in the same RBA or (2) to place the next packet in

another RBA If the EOBC is less than or equal to the re-

maining number of words in the RBA after a packet is re-

ceived (ie EOB s RBWC01) the SONIC buffers the next

packet in the same RBA If the EOBC is greater than

the remaining number of words in the RBA after a packet is

received (ie EOBC l RBWC01) the Last Packet in RBA

bit LPKT in the Receive Control Register Section 433 is

set and the SONIC fetches the next resource descriptor

Hence the next packet received will be buffered in a new

RBA A hardware reset sets this register to 02F8H (760

words or 1520 bytes) See Sections 342 and 3444 for

more information about using EOBC

Upper Receive Resource Address Register (URRA)

The

URRA is a 16-bit readwrite register It is programmed with

the base address of the receive resource area (RRA) This

16-bit upper address value (Ak3116l) locates the receive

resource area in system memory SONIC uses the URRA

RRA by concatenating the lower address value from one of

four receive resource registers (RSA REA RWP or RRP)

Resource Start Address Register (RSA)

The RSA is a

15-bit readwrite register The LSB is not used and always

reads back as a 0 The RSA is programmed with the lower

15-bits (Ak151l) of the starting address of the receive

resource area SONIC concatenates the contents of this

32-bit address

Resource End Address Register (REA)

The REA is a

15-bit readwrite register The LSB is not used and always

reads back as a 0 The REA is programmed with the lower

15-bits (Ak151l) of the ending address of the receive re-

source area SONIC concatenates the contents of this reg-

ister with the contents of the URRA to form the complete

32-bit address

Resource Read Pointer Register (RRP)

The RRP is a

15-bit readwrite register The LSB is not used and always

reads back as a 0 The RRP is programmed with the lower

15-bit address (Ak151l) of the first field of the next de-

scriptor the SONIC will read SONIC concatenates the con-

tents of this register with the contents of the URRA to form

the complete 32-bit address

Resource Write Pointer Register (RWP)

The RWP is a

15-bit readwrite register The LSB is not used and always

reads back as a 0 The RWP is programmed with the lower

15-bit address (Ak151l) of the next available location the

system can add a descriptor SONIC concatenates the con-

tents of this register with the contents of the URRA to form

the complete 32-bit address In 32-bit mode bit 1 corre-

sponding to address signal A1 must be zero to insure the

proper equality comparison between this register and the

RRP register

Receive Sequence Counter Register (RSC)

This is a

16-bit readwrite register containing two fields The SONIC

uses this register to provide status information on the num-

ber of packets within a RBA and the number of RBAs The

RSC register contains two 8-bit (modulo 256) counters Af-

ter each packet is received the packet sequence number is

incremented The SONIC maintains a single sequence num-

ber for each RBA When the SONIC uses the next RBA the

packet sequence number is reset to zero and the RBA se-

quence number is incremented This register is reset to 0 by

a hardware reset or by writing zero to it A software reset

has no affect

RBA Sequence Number

Packet Sequence Number

(Modulo 256)

DP83932C Datasheet(PDF) 40 Page - National Semiconductor (TI)

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