DP83932C datasheet(63/98 Pages) NSC

63 / 98 page

50 Bus Interface (Continued)

TLF10492 – 46

FIGURE 5-20 Bus Exception (Bus Retry)

Latched Bus Retry is set though the SONIC will not retry

until the BR bit in the ISR (see Section 436) has been reset

and BRT is deasserted BRT has precedence of terminating

a memory cycle over DSACK01 STERM or RDYi

BRT may be sampled synchronously or asynchronously by

setting the EXBUS bit in the DCR (see Section 432) If

synchronous Bus Retry is set BRT is sampled on the rising

edge of T2 If asynchronous Bus Retry is set BRT is double

synchronized from the falling edge of T1 The asynchronous

setup time does not need to be met but doing so will guar-

antee that the bus exception will occur in the current bus

cycle instead of the next bus cycle Asynchronous Bus Re-

try may only be used when the SONIC is set to asynchro-

nous mode

Note 1

The deassertion edge of HOLD is dependent on the PH bit in the

DCR2 (see Section 437) Also BGACK is driven high for about

bus clock before going TRI-STATE

Note 2

If Latched Bus Retry is set BRT need only satisfy its setup time

(the hold time is not important) Otherwise BRT must remain as-

serted until after the Th state

Note 3

If DSACK01 STERM or RDYi remain asserted after BRT the next

memory cycle may be adversely affected

547 Slave Mode Bus Cycle

The SONIC’s internal registers can be accessed by one of

two methods (BMODE e 1 or BMODE e 0) In both meth-

ods the SONIC is a slave on the bus This section de-

scribes the SONIC’s slave mode bus operations

5471 Slave Cycle for BMODE e 1

The system accesses the SONIC by driving SAS CS SRW

and RAk50l SONIC will start a slave cycle once CS and

SAS are asserted properly SONIC samples CS asynchro-

nously at the falling edge of each BSCK SAS signal can be

asserted anytime as long as it is before the next falling edge

of the clock that the CS is sampled on

The register address RAk50l and the readwrite signal

SRW will be latched by the SONIC on the falling edge of the

SAS signal Once SAS and CS are asserted SMACK will be

asserted by the SONIC to signify that the SONIC has started

the slave cycle Although CS and SAS are asynchronous

inputs meeting their setup times (as shown in

Figures 5-21

and

5-22 ) will guarantee that SMACK which is asserted off

of a falling edge will be asserted 1 bus clock after the falling

edge that CS was clocked in on This is assuming that the

SONIC is not a bus master when CS was asserted If the

SONIC is a bus master then when CS is asserted the

SONIC will complete its current master bus cycle and get off

the bus temporarily (see Section 548)

In this case

SMACK will be asserted maximum 5 bus clocks after the

falling edge that CS was clocked in on This is assuming

that there were no wait states in the current master mode

access Wait states will increase the time for SMACK to go

low by the number of wait states in the cycle

If the slave access is a read cycle (

Figure 5-21 ) then the

data will be driven off the same edge as SMACK Ifitisa

write cycle (

Figure 5-22 ) then the data will be latched in

exactly 2 bus clocks after the assertion of SMACK In either

case DSACK01 are driven low 2 bus clocks after SMACK

to terminate the slave cycle For a read cycle the assertion

of DSACK01 indicates valid register data and for a write

cycle the assertion indicates that the SONIC has latched

the data The SONIC deasserts DSACK01 at the rising

edge of SAS or CS depending on which is deasserted first

The data bus is deasserted on the rising edge of SAS The

SONIC deasserts SMACK and causes DSACK01 to be-

come TRI-STATE on the falling edge of the BSCK that SAS

was sampled high on

Note 1

Although the SONIC responds as a 32-bit peripheral when it drives

both DSACK0 and DSACK1 low it transfers data only on lines

Dk150l

Note 2

For multiple register accesses CS can be held low and SAS can be

used to delimit the slave cycle In this case SMACK will be driven

low due to SAS going low since CS has already been asserted

Notice that this means SMACK will not stay asserted low during the

entire time CS is low (as is the case for MREQ Section 548)

Note 3

If memory request (MREQ) follows a chip select (CS) it must be

asserted at least 2 bus clocks after CS is deasserted Both CS and

MREQ must not be asserted concurrently

Note 4

When CS is deasserted it must remain deasserted for at least one

bus clock

Note 5

The way in which SMACK is asserted due to CS is not the same as

the way in which SMACK is asserted due to MREQ The assertion

of SMACK is dependent upon both CS and SAS being low not just

CS This is not the same as the case for MREQ (see Section 548)

The assertion of SMACK in these two cases should not be con-

fused

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