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DP83932C Datasheet(PDF) 74 Page - National Semiconductor (TI) |
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DP83932C Datasheet(HTML) 74 Page - National Semiconductor (TI) |
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74 / 98 page  70 AC and DC Specifications (Continued) MEMORY WRITE BMODE e 0 SYNCHRONOUS MODE (one wait-state shown) TLF10492 – 59 Number Parameter 20 MHz 25 MHz 33 MHz Units Min Max Min Max Min Max T9 BSCK to Address ValidHold Time 3 26 3 24 3 22 ns T11 BSCK to ADS Low 26 24 22 ns T11b BSCK to ECS Low 19 17 15 ns T12 BSCK to ADS High 24 22 20 ns T12b BSCK to ECS High 29 27 25 ns T15 ADS High Width 45 35 25 ns T32 RDYi Setup to BSCK 19 17 15 ns T33 RDYi Hold from BSCK 5 3 3 ns T36 BSCK to Memory Write Data 350348346 ns ValidHold Time (Note 2) T37 BSCK to MWR (Write) Valid (Note 1) 24 22 20 ns Note 1 For successive write operations MWR remains high Note 2 One idle clock cycle (Ti) will be inserted between the last write cycle and the following read cycle in RDA and TDA operation Note that the data bus will become TRI-STATE from the rising edge of the clock after the idle cycle (see T52 for BSCK to data TRI-STATE timing) 74 |
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