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DP83932C Datasheet(PDF) 60 Page - National Semiconductor (TI) |
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DP83932C Datasheet(HTML) 60 Page - National Semiconductor (TI) |
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60 / 98 page  50 Bus Interface (Continued) 5454 Memory Cycle for BMODE e 0 Synchronous Mode On the rising edge of T1 the SONIC asserts ADS and ECS to indicate that the memory cycle is starting The address (A31-A1) bus status (S2-S0) and the direction strobe (MWR) are driven and do not change for the remainder of the memory cycle On the falling edge of T1 the SONIC deasserts ECS ADS is deasserted on the rising edge of T2 In Synchronous mode RDYi is sampled on the rising edge at the end of T2 (the rising edge of the next T1) T2 states will be repeated until RDYi is sampled properly in a low state RDYi must meet the setup and hold times with re- spect to the rising edge of bus clock for proper operation During read cycles ( Figure 5-14 ) data (D31-D0) is latched at the rising edge at the end of T2 For write cycles ( Figure 5-15 ) data is driven on the rising edge of T1 and stays driv- en until the end of the cycle TLF10492 – 38 FIGURE 5-14 Memory Read BMODEe0 Synchronous (1 Wait-State) TLF10492 – 40 FIGURE 5-15 Memory Write BMODEe0 Synchronous (1 Wait-State) 60 |
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