DP83932C datasheet(7/98 Pages) NSC

7 / 98 page

10 Functional Description (Continued)

Serializer

After data has been written into the 32-byte

transmit FIFO the serializer reads byte wide data from the

FIFO and sends a NRZ data stream to the Manchester en-

coder The rate at which data is transmitted is determined

by the transmit clock (TXC) The serialized data is transmit-

ted after the SFD

Preamble Generator

The preamble generator prefixes a 7

byte alternating ‘‘10’’ pattern and a 1 byte ‘‘10101011’’

SFD pattern at the beginning of each packet This allows

receiving nodes to synchronize to the incoming data The

preamble is always transmitted in its entirety even in the

event of a collision This assures that the minimum collision

fragment is 96 bits (64 bits of normal preamble and 4 bytes

or rather 32 bits of the JAM pattern)

CRC Generator

The CRC generator calculates the 4-byte

FCS field from the transmitted serial data stream If en-

abled the 4-byte FCS field is appended to the end of the

transmitted packet (Section 26)

For bridging or switched ethernet applications the CRC

Generator can be inhibited by setting bit 13 in the Transmit

Control Register (Section 434) This feature is used when

an ethernet segment has already received a packet with a

CRC appended and needs to forward it to another ethernet

segment

Jam Generator

The Jam generator produces a 4-byte pat-

tern of all 1’s to assure that all nodes on the network sense

the collision When a collision occurs the SONIC stops

transmitting data and enables the Jam generator If a colli-

sion occurs during the preamble the SONIC finishes trans-

mitting the preamble before enabling the Jam generator

(see Preamble Generator above)

13 DATA WIDTH AND BYTE ORDERING

The SONIC can be programmed to operate with either

32-bit or 16-bit wide memory The data width is configured

during initialization by programming the DW bit in the Data

Configuration Register (DCR Section 432) If the 16-bit

data path is selected data is driven on pins D15 – D0 The

SONIC also provides both Little Endian and Big Endian

byte-ordering capability for compatibility with NationalIntel

or Motorola microprocessors respectively by selecting the

proper level on the BMODE pin The byte ordering is depict-

ed below

Little Endian mode (NationalIntel BMODE e 0) The

byte orientation for received and transmitted data in the Re-

ceive Buffer Area (RBA) and Transmit Buffer Area (TBA) of

system memory is as follows

16-Bit Word

Byte 1

Byte 0

MSB

LSB

32-Bit Long Word

Byte 3

Byte 2

Byte 1

Byte 0

MSB

LSB

Big Endian mode (Motorola BMODE e 1)

The byte ori-

entation for received and transmitted data in the RBA and

TBA is as follows

16-Bit Word

Byte 0

Byte 1

LSB

MSB

32-Bit Long Word

Byte 0

Byte 1

Byte 2

Byte 3

LSB

MSB

TLF10492 – 6

FIGURE 1-5 Receive FIFO

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