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DP83932C Datasheet(PDF) 59 Page - National Semiconductor (TI) |
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DP83932C Datasheet(HTML) 59 Page - National Semiconductor (TI) |
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59 / 98 page  50 Bus Interface (Continued) bus clocks after DSACK01 were sampled or 1 cycle after STERM was sampled T2 states will be repeated until DSACK01 or STERM are sampled properly in a low state (see note below) During read cycles ( Figures 5-10 and 5-11 ) data (D31-D0) is latched at the falling edge of T2 and DS is asserted at the falling edge of T1 For write cycles ( Figures 5-12 and 5-13 ) data is driven on the rising edge of T1 If there are wait states inserted DS is asserted on the falling edge of the first T2 (wait) DS is not asserted for zero wait state write cycles The SONIC terminates the memory cycle by deasserting AS and DS at the falling edge of T2 Note If the setup time for DSACK01 is met during T1 or the setup time for STERM is met during the first T2 the full asynchronous bus cycle will take only 2 bus clocks This may be an unwanted situation If so DSACK01 and STERM should normally be deasserted during T1 and the start of T2 respectively TLF10492 – 34 FIGURE 5-12 Memory Write BMODEe1 Asynchronous (1 Wait-State) TLF10492 – 35 FIGURE 5-13 Memory Write BMODEe1 Asynchronous (2 Wait-State) 59 |
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