DP83932C datasheet(50/98 Pages) NSC

50 / 98 page

50 Bus Interface (Continued)

TABLE 5-1 Pin Description

(Continued)

Symbol

Driver

Direction

Description

Type

SHARED-MEMORY ACCESS PINS

MREQ

Memory Request

The system asserts this signal low when it attempts to access the

shared-buffer RAM The on-chip arbiter resolves accesses between the system and the

SONIC

Note

Both CS and MREQ must not be asserted concurrently If these signals are

successively asserted there must be at least two bus clocks between the deasserting

edge of the first signal and the asserting edge of the second signal

In Motorola mode if a bus master uses the MREQ to request the bus from the SONIC

care should be taken to isolate the DSACK01 from the bus (eg use tri-state buffers)

because the DSACK01 will be driven by the SONIC even after the SONIC has given up

the bus

SMACK

Slave and Memory Acknowledge

SONIC asserts this dual function pin low in

response to either a Chip Select (CS) or a Memory Request (MREQ) when the SONIC’s

registers or its buffer memory is available for accessing This pin can be used for

enabling bus drivers for dual-bus systems

USER DEFINABLE PINS

USR01

TRI

I O Z

User Define 01

These signals are inputs when SONIC is hardware reset and are

outputs when SONIC is a bus master (HLDA or BGACK asserted) When hard reset

(RST) is low these signals input directly into bits 8 and 9 of the Data Configuration

RST During busmaster operations (HLDA or BGACK is active) these pins are outputs

whose levels are programmable through bits 11 and 12 of the DCR respectively The

USR01 pins should be pulled up to VCC or pulled down to ground A 47 kX pull-up

resistor is recommended

POWER AND GROUND PINS

VCC1 – 5

Power

The a5V power supply for the digital portions of the SONIC

VCCL

TXVCC

Power

These pins are the a5V power supply for the SONIC ENDEC unit These pins

must be tied to VCC even if the internal ENDEC is not used

RXVCC

PLLVCC

GND1 – 6

Ground

The ground reference for the digital portions of the SONIC

GNDL

TXGND

Ground

These pins are the ground references for the SONIC ENDEC unit These pins

must be tied to ground even if the internal ENDEC is not used

ANGND

53 SYSTEM CONFIGURATION

Any device that meets the SONIC interface protocol and

electrical requirements (timing threshold and loading) can

be interfaced to SONIC Since two bus protocols are provid-

ed via the BMODE pin the SONIC can interface directly to

most microprocessors

Figure 5-3 shows a typical interface

to the NationalIntel style bus (BMODEe0) and

Figure 5-4

shows a typical interface to the Motorola style bus

(BMODEe1)

The BMODE pin also controls byte ordering

When

BMODEe1 big endian byte ordering is selected and when

BMODEe0 little endian byte ordering is selected

54 BUS OPERATIONS

There are two types of system bus operations 1) SONIC as

a slave and 2) SONIC as a bus master When SONIC is a

slave (eg a CPU accessing SONIC registers) all transfers

are non-DMA When SONIC is a bus master (eg SONIC

accessing receive or transmit bufferdescriptor areas) all

transfers are block transfers using SONIC’s on-chip DMA

This section describes the SONIC bus operations Pay spe-

cial attention to all sections labeled as ‘‘Note’’ These con-

ditions must be met for proper bus operation

DP83932C Datasheet(PDF) 50 Page - National Semiconductor (TI)

DP83932C Datasheet(HTML) 50 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

Datasheet Download

Link URL