DP83932C datasheet(85/98 Pages) NSC

85 / 98 page

70 AC and DC Specifications (Continued)

BUS REQUEST TIMING BMODE e 1

TLF10492 – 68

Number

Parameter

20 MHz

25 MHz

33 MHz

Units

Min

Max

Min

Max

Min

Max

T45a

BG AS BGACK DSACK01 and STERM

765

Asynchronous Setup Time to BSCK (Note 1)

T51a

BSCK to Address AS MRW DS ECS

USRk10l and EXUSRk30l TRI-STATE

T52

BSCK to Data TRI-STATE

T53

BSCK to Address AS MRW DS ECS

USRk10l and EXUSRk30l Active (Note 1)

T54

BSCK Low to BR LowTRI-STATE

T54a

BSCK High to BGACK LowHigh

T54b

BSCK High to BGACK TRI-STATE

T55

BSCK to Bus Status Valid

T55b

Sk20l Hold from BSCK

Note 1

BGACK is asserted one bus clock after all the signals (AS DSACK01 BGACK STERM (Extended bus mode) and BG) meet the T45a setup time (see

Section 541 for more information) The address bus AS DS ECS MRW USRk10l and EXUSRk30l will also be driven active on the same clock

Note 2

Sk20l will indicate IDLE at the end of T2 if the last operation is a read operation or at the end of Th if the last operation is a write operation

DP83932C Datasheet(PDF) 85 Page - National Semiconductor (TI)

DP83932C Datasheet(HTML) 85 Page - National Semiconductor (TI)

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