DP83932C datasheet(42/98 Pages) NSC

42 / 98 page

40 SONIC Registers (Continued)

4312 General Purpose Timer

The SONIC contains a 32-bit general-purpose Watchdog

Timer for timing user-definable events This timer is ac-

cessed by the user through two 16-bit readwrite registers

(WT1 and WT0) The lower count value is programmed

through the WT0 register and the upper count value is pro-

grammed through the WT1 register

These two registers are concatenated together to form the

complete 32-bit timer This timer clocked at

the Transmit

Clock (TXC) frequency counts down from its programmed

value and generates an interrupt if enabled (Interrupt Mask

FFFFh When the counter rolls over it continues decrement-

ing unless explicitly stopped (setting the STP bit) The timer

is controlled by the ST (Start Timer) and STP (Stop Timer)

bits in the Command register A hardware or software reset

halts but does not clear the General Purpose timer

WT1 (Upper Count Value)

WT0 (Lower Count Value)

4313 Silicon Revision Register

This is a 16-bit read only register It contains information on

the current revision of the SONIC

The value of the

DP83932CVF revision register is 6h

50 Bus Interface

SONIC features a high speed non-multiplexed address and

data bus designed for a wide range of system environments

The data bus can be programmed (via the Data Configura-

tion Register) to a width of either 32- or 16-bits SONIC con-

tains an on-chip DMA and supplies all the necessary signals

for DMA operation With 31 address lines SONIC can ac-

cess a full 2 G-word address space To accommodate dif-

ferent memory speeds wait states can be added to the bus

cycle by two methods The memory subsystem can add wait

states by simply withholding the appropriate handshake sig-

nals In addition the SONIC can be programmed (via the

Data Configuration Register) to add wait states

The SONIC is designed to interface to both the NationalIn-

tel and Motorola style buses To facilitate minimum chip

count designs and complete bus compatibility the user can

program the SONIC for the following bus modes

NationalIntel bus operating in synchronous mode

NationalIntel bus operating in asynchronous mode

Motorola bus operating in synchronous mode

Motorola bus operating in asynchronous mode

The mode pin (BMODE) along with the SBUS bit in the Data

Configuration Register are used to select the bus mode

This section describes the SONIC’s pin signals provides

system interface examples

and describes the various

SONIC bus operations

51 PIN CONFIGURATIONS

There are two user selectable pin configurations for SONIC

to provide the proper interface signals for either the Nation-

alIntel or Motorola style buses The state of the BMODE

pin is used to define the pin configuration

Figure 5-1 shows

the pin configuration when BMODEe1 (tied to VCC) for the

Motorola style bus

Figure 5-2 shows the pin configuration

when BMODEe0 (tied to ground) for the NationalIntel

style bus

DP83932C Datasheet(PDF) 42 Page - National Semiconductor (TI)

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