DP83932C datasheet(65/98 Pages) NSC

65 / 98 page

50 Bus Interface (Continued)

5472 Slave Cycle for BMODE e 0

The system accesses the SONIC by driving SAS CS SWR

and RAk50l SONIC will start a slave cycle once CS and

SAS are asserted properly SONIC samples CS asynchro-

nously at the falling edge of each BSCK SAS signal may be

asserted low anytime before or simultaneously to the falling

edge of the CS and the deassertion of SAS will start the

slave cycle CS should not be asserted low before the falling

edge of SAS as this will cause improper slave operation

The register address RAk50l and the readwrite signal

SWR will be latched by the SONIC on the rising edge of the

SAS signal Once CS is asserted and SAS is deasserted

SMACK will be asserted by the SONIC to signify that the

SONIC has started the slave cycle Although CS and SAS

are asynchronous inputs meeting their setup times (as

shown in

Figures 5-23 and 5-24 ) will guarantee that

SMACK which is asserted off a falling edge will be assert-

ed on the falling edge of the BSCK and SAS was sampled

high on This is assuming that the SONIC is not a bus mas-

ter when CS is asserted If the SONIC is a bus master then

when CS is asserted the SONIC will complete its current

master bus cycle and get off the bus temporarily (see Sec-

tion 548) In this case SMACK will be asserted maximum 4

bus clocks after the falling edge of BSCK that SAS was

sampled high on This is assuming that there were no wait

states in the current master mode access Wait states will

increase the time for SMACK to go low by the number of

wait states in the cycle

If the slave access is a read cycle (

Figure 5-23 ) then the

data will be driven off the same edge as SMACK Ifitisa

write cycle (

Figure 5-24 ) then the data will be latched in

exactly 2 bus clocks after the assertion of SMACK In either

case RDYo is driven low 25 bus clocks after SMACK to

terminate the slave cycle For a read cycle the assertion of

RDYo indicates valid register data and for a write cycle the

assertion indicates that the SONIC has latched the data

The SONIC deasserts RDYo SMACK and the data if the

cycle is a read cycle at the falling edge of SAS or the rising

edge of CS depending on which is first

Note 1

The SONIC transfers data only on lines Dk150l during slave

mode accesses

Note 2

For multiple register accesses CS can be held low and SAS can be

used to delimit the slave cycle (this is the only case where CS may

be asserted before SAS) In this case SMACK will be driven low

due to SAS going high since CS has already been asserted Notice

that this means SMACK will not stay asserted low during the entire

time CS is low (as is the case for MREQ see Section 548)

Note 3

If memory request (MREQ) follows a chip select CS it must be

asserted at least 2 bus clocks after CS is deasserted Both CS and

MREQ must not be asserted concurrently

Note 4

When CS is deasserted it must remain deasserted for at least one

bus clock

Note 5

The way in which SMACK is asserted due to CS is not the same as

the way in which SMACK is asserted due to MREQ The assertion of

SMACK is dependent upon both CS and SAS being low not just CS

This is not the same as the case for MREQ (see Section 548) The

assertion of SMACK in these two cases should not be confused

TLF10492 – 49

FIGURE 5-23 Register Read BMODEe0

DP83932C Datasheet(PDF) 65 Page - National Semiconductor (TI)

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