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DP83932C Datasheet(PDF) 73 Page - National Semiconductor (TI) |
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DP83932C Datasheet(HTML) 73 Page - National Semiconductor (TI) |
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73 / 98 page ![]() 70 AC and DC Specifications (Continued) AC Characteristics BUS CLOCK TIMING TLF10492 – 56 Number Parameter 20 MHz 25 MHz 33 MHz Units Min Max Min Max Min Max T1 Bus Clock Low Time 20 16 135 ns T2 Bus Clock High Time 20 16 135 ns T3 Bus Clock Cycle Time 50 40 30 ns POWER-ON RESET TLF10492 – 57 NON POWER-ON RESET TLF10492 – 58 Number Parameter 20 MHz 25 MHz 33 MHz Units Min Max Min Max Min Max T4 USRk10l Setup to RST 765 ns T5 USRk10l Hold from RST 987 ns T6 Power-On Reset Low (Notes 1 2) 10 10 10 TXC T8 Reset Pulse Width (Notes 1 2) 10 10 10 TXC Note 1 The reset time is determined by the slower of BSCK or TXC If BSCK l TXC T6 and T8 equal 10 TXCs If BSCK k TXC T6 and T8 equal 10 BSCKs (T3) Note 2 These specifications are not tested 73 |
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