DP83932C datasheet(55/98 Pages) NSC

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50 Bus Interface (Continued)

5431 Bus Status Transitions

When the SONIC acquires the bus it only transfers data

tofrom a single area in memory (ie TDA TBA RDA RBA

RRA or CDA) Thus the bus status pins remain stable for

the duration of the block transfer cycle with the following

three exceptions 1) If the SONIC is accessed during a block

transfer S2 – S0 indicates bus idle during the register ac-

cess then returns to the previous status 2) If the SONIC

finishes writing the Source Address during a block transfer

S2 – S0 changes from 010 to 011

3) During an RDA

access between the RXpktseq

no and RXpktlink access

and between the RXpktlink and RXpktin

use access

S2 – S0 will respectively indicate idle 111 for2or1bus

clocks Status will be valid on the falling edge of AS or rising

edge of ADS

Figure 5-7 illustrates the SONIC’s transitions through mem-

ory during the process of transmission and reception Dur-

ing transmission the SONIC reads the descriptor informa-

tion from the TDA and then transmits data of the packet

from the TBA The SONIC moves back and forth between

the TDA and TBA until all fragments and packets are trans-

mitted During reception the SONIC takes one of two paths

In the first case (path A) when the SONIC detects EOLe0

from the previous reception it buffers the accepted packet

into the RBA and then writes the descriptor information to

the RDA If the RBA becomes depleted (ie RBWC01 k

EOBC) it moves to the RRA to read a resource descriptor

In the second case (path B) when the SONIC detects

EOLe1 from the previous reception

it rereads the

RXpktlink field to determine if the system has reset the EOL

bit since the last reception If it has the SONIC buffers the

packet as in the first case Otherwise it rejects the packet

and returns to idle

544 Bus Mode Compatibility

For compatibility with different microprocessor and bus ar-

chitectures the SONIC operates in one of two modes (set

by the BMODE pin) called the NationalIntel or little endian

mode (BMODE tied low) and the Motorola or big endian

mode (BMODE tied high) The definitions for several pins

change depending on the mode the SONIC is in Table 5-3

shows these changes These modes affect both master and

slave bus operations with the SONIC

TABLE 5-3 Bus Mode Compatibility

Pin Name

BMODEe0

BMODEe1

(NationalIntel)

(Motorola)

BR HOLD

HOLD

BG HLDA

HLDA

MRW MWR

MWR

MRW

SRW SWR

SWR

SRW

DSACK0 RDYi

RDYi

DSACK0

DSACK1 RDYo

RDYo

DSACK1

AS ADS

ADS

INT INT

INT

TLF10492 – 29

FIGURE 5-7 Bus Status Transitions

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