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DP83932C Datasheet(PDF) 81 Page - National Semiconductor (TI) |
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DP83932C Datasheet(HTML) 81 Page - National Semiconductor (TI) |
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81 / 98 page  70 AC and DC Specifications (Continued) Number Parameter 20 MHz 25 MHz 33 MHz Units Min Max Min Max Min Max T9 BSCK to Address Valid 3 26 3 24 3 22 ns T11a BSCK to AS Low 17 15 13 ns T11c BSCK to ECS Low 19 17 15 ns T12a BSCK to AS High 17 15 13 ns T12c BSCK to ECS High 19 17 15 ns T13a BSCK to DS Low 16 14 12 ns T13b BSCK to DS High 16 14 12 ns T14 AS Low Width 44 34 24 ns T15a AS High Width 45 35 25 ns T18 Write Data Strobe Low Width (Note 3) 40 30 20 ns T19 Address Hold Time from AS 18 14 10 ns T20 Data Hold Time from AS 20 16 12 ns T22 Address Valid to AS 962 ns T30 DSACK01 Setup to BSCK (Note 2) 5 4 3 ns T30a STERM Setup to BSCK (Note 2) 5 4 3 ns T31 DSACK01 Hold from BSCK 9 8 7 ns T31a STERM Hold from BSCK 8 7 6 ns T36 BSCK to Memory Write Data Valid (Note 4) 3 50 3 48 3 46 ns T37a BSCK to MRW (Write) Valid (Note 1) 26 24 22 ns T39 Write Data Valid to Data Strobe Low 34 21 7 ns Note 1 For successive write operations MRW remains low Note 2 Meeting the setup time for DSACK01 or STERM guarantees that the SONIC will terminate the memory cycle 1 bus clocks after DSACK01 were sampled or 1 cycle after STERM was sampled T2 states will be repeated until DSACK01 or STERM are sampled properly in a low state If the SONIC samples DSACK01 or STERM low during the T1 or first T2 state respectively the SONIC will finish the current access in a total of two bus clocks instead of three (assuming that programmable wait states are set to 0) DSACK01 are asynchronously sampled and STERM is synchronously sampled Note 3 DS will only be asserted if the bus cycle has at least one wait state inserted Note 4 One idle clock cycle (Ti) will be inserted between the last write cycle and the following read cycle in RDA and TDA operation Note that the data bus will become TRI-STATE from the rising edge of the clock after the idle cycle (see T52 for BSCK to data TRI-STATE timing) 81 |
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