DP83932C datasheet(87/98 Pages) NSC

87 / 98 page

70 AC and DC Specifications (Continued)

MEMORY ARBITRATIONSLAVE ACCESS

TLF10492 – 70

Number

Parameter

20 MHz

25 MHz

33 MHz

Units

Min

Max

Min

Max

Min

Max

T56

CS Low Asynch Setup to BSCK

876

(Note 2)

T58

MREQ Low Asynch Setup to BSCK

876

(Note 2)

T60

MREQ or CS Valid to SMACK Low

151515

bcyc

(Notes 3 4)

T80

MREQ to SMACK High

T81

BSCK to SMACK Low

Note 1

Both CS and MREQ must not be asserted concurrently If these signals are successively asserted there must be at least two bus clocks between the

deasserting and asserting edges of these signals

Note 2

It is not necessary to meet the setup times for MREQ or CS since these signals are asynchronously sampled Meeting the setup time for these signals

however makes it possible to use T60 to determine when SMACK will be asserted

Note 3

T60 could range from 1 bus clock minimum to 5 bus clock maximum depending on what state machine the SONIC is in when the CS or MREQ signal is

asserted This timing is not tested but is guaranteed by design This specification assumes that CS or MREQ is asserted before the falling edge that these signals

are asynchronously clocked in on (see T56 and T58) SAS must have been asserted for this timing to be correct See SAS and CS timing in the Register Read and

Note 4

bcyc e bus clock cycle time (T3)

Note 5

The way in which SMACK is asserted due to CS is not the same as the way in which SMACK is asserted due to MREQ SMACK goes low as a direct result

of the assertion of MREQ whereas for CS SAS must also be driven low (BMODE e 1) or high (BMODE e 0) before SMACK will be asserted This means that

when SMACK is asserted due to MREQ SMACK will remain asserted until MREQ is deasserted Multiple memory accesses can be made to the shared memory

without SMACK ever going high When SMACK is asserted due to CS however SMACK will only remain low as long as SAS is also low (BMODE e 1) or high

(BMODE e 0) SMACK will not remain low throughout multiple register accesses to the SONIC because SAS must toggle for each register access This in an

important difference to consider when designing shared memory designs

DP83932C Datasheet(PDF) 87 Page - National Semiconductor (TI)

DP83932C Datasheet(HTML) 87 Page - National Semiconductor (TI)

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