DP83932C datasheet(68/98 Pages) NSC

68 / 98 page

50 Bus Interface (Continued)

13 Latched Ready Mode is disabled (DCR2)

14 PCOMP will not be asserted (DCR2)

15 Packets will be accepted (not rejected) on CAM match

(DCR2)

A software reset immediately terminates DMA operations

and future interrupts The chip is put into an idle state where

registers can be accessed but the SONIC will not be active

in any other way The registers are affected by a software

reset as shown in Table 5-4 (only the Command Register is

changed)

60 Network Interfacing

The SONIC contains an on-chip ENDEC that performs the

network interfacing between the AUI (Attachment Unit Inter-

face) and the SONIC’s MAC unit A pin selectable option

allows the internal ENDEC to be disabled and the MAC

ENDEC signals to be supplied to the user for connection to

an external ENDEC If the EXT pin is tied to ground

(EXTe0) the internal ENDEC is selected and if EXT is tied

to VCC (EXTe1) the external ENDEC option is selected

Internal ENDEC

When the internal ENDEC is used

(EXTe0) the interface signals between the ENDEC and

MAC unit are internally connected While these signals are

used internally by the SONIC they are also provided as an

output to the user

(Figure 6-1 )

The internal ENDEC allows for a 2-chip solution for the

complete Ethernet interface

Figure 6-2 shows a typical dia-

gram of the network interface

TLF10492 – 52

FIGURE 6-1 MAC and Internal ENDEC Interface Signals

DP83932C Datasheet(PDF) 68 Page - National Semiconductor (TI)