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WM5102 Datasheet(PDF) 110 Page - Wolfson Microelectronics plc |
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WM5102 Datasheet(HTML) 110 Page - Wolfson Microelectronics plc |
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110 / 334 page  WM5102 Production Data w PD, June 2014, Rev 4.2 110 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3827 (0EF3h) ISRC 2 CTRL 1 14:11 ISRC2_FSH [3:0] 0000 ISRC2 High Sample Rate (Sets the higher of the ISRC2 sample rates) 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. The ISRC2_FSH and ISRC2_FSL fields must both select sample rates referenced to the same clock domain (SYSCLK or ASYNCCLK). R3828 (0EF4h) ISRC 2 CTRL 2 14:11 ISRC2_FSL [3:0] 0000 ISRC2 Low Sample Rate (Sets the lower of the ISRC2 sample rates) 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. The ISRC2_FSH and ISRC2_FSL fields must both select sample rates referenced to the same clock domain (SYSCLK or ASYNCCLK). R3829 (0EF5h) ISRC 2 CTRL 3 15 ISRC2_INT1_EN A 0 ISRC2 INT1 Enable (Interpolation Channel 1 path from ISRC2_FSL rate to ISRC2_FSH rate) 0 = Disabled 1 = Enabled 14 ISRC2_INT2_EN A 0 ISRC2 INT2 Enable (Interpolation Channel 2 path from ISRC2_FSL rate to ISRC2_FSH rate) 0 = Disabled 1 = Enabled 9 ISRC2_DEC1_EN A 0 ISRC2 DEC1 Enable (Decimation Channel 1 path from ISRC2_FSH rate to ISRC2_FSL rate) 0 = Disabled 1 = Enabled 8 ISRC2_DEC2_EN A 0 ISRC2 DEC2 Enable (Decimation Channel 2 path from ISRC2_FSH rate to ISRC2_FSL rate) 0 = Disabled 1 = Enabled 0 ISRC2_NOTCH_ ENA 0 ISRC2 Notch Filter Enable 0 = Disabled 1 = Enabled It is recommended to enable the notch filter for typical applications. Table 23 Digital Core ISRC Control |
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