WM5102 datasheet(113/334 Pages) WOLFSON

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WM5102

PD, June 2014, Rev 4.2

113

DSP FIRMWARE EXECUTION

After the DSP firmware has been loaded, and the clocks configured, the DSP block is enabled using

the DSP1_CORE_ENA and DSP1_START register bits. Write ‘1’ to both registers to enable and start

the firmware execution.

The DSP1_CORE_ENA bit must be set to ‘1’ to enable DSP firmware execution. Note that the usage

of the DSP1_START bit may vary depending on the particular software that is being executed: in

some applications, writing to the DSP1_START bit will not be required.

For read/write access to the DSP firmware memory registers, the respective firmware execution must

be disabled by setting the DSP1_CORE_ENA bit to ‘0’.

The audio signal paths connecting to/from the DSP processing blocks are configured as described in

the “Digital Core” section. Note that the DSP firmware must be loaded and enabled before audio

signal paths can be enabled.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4352

(1100h)

DSP1

Control 1

DSP1_CORE_EN

DSP1 Enable

Controls the DSP1 firmware execution

0 = Disabled

1 = Enabled

DSP1_START

DSP1 Start

Write ‘1’ to Start DSP1 firmware execution

Table 26 DSP Firmware Execution

DSP DIRECT MEMORY ACCESS (DMA) CONTROL

The DSP provides a multi-channel DMA function; this is configured using the registers described in

Table 27.

There are 8 WDMA channels and 6 RDMA channels; these are enabled using the

DSP1_WDMA_CHANNEL_ENABLE and DSP1_RDMA_CHANNEL_ENABLE fields.

Note that, after disabling the DSP (ie. writing DSP1_CORE_ENA=0), the associated DMA must be

disabled by setting the DSP1_WDMA_BUFFER_LENGTH, DSP1_WDMA_CHANNEL_ENABLE, and

DSP1_RDMA_CHANNEL_ENABLE fields to 00h.

The DMA can access the X data memory or Y data memory associated with the DSP. The applicable

memory is selected using bit [15] of the respective *_START_ADDRESS register.

The start address of each DMA channel is configured as described in Table 27. Note that the required

address is defined relative to the base address of the selected (X data or Y data) memory.

The buffer length of the WDMA channels is configured using the DSP1_WDMA_BUFFER_LENGTH

field. The selected buffer length applies to all enabled WDMA channels.

Note that the start address registers, and WDMA buffer length registers, are defined in 24-bit DSP

data word units. This means that the LSB of these fields represents one 24-bit DSP memory word.

(Note that this differs from the WM5102 register map layout, as described in Table 24).

The parameters of a DMA channel (ie. Start Address) must not be changed whilst the respective DMA

is enabled. All of the WDMA channels must be disabled before changing the WDMA buffer length.

Further details of the DMA are provided in the software programming guide - please contact your local

Wolfson representative if required.

WM5102 Datasheet(PDF) 113 Page - Wolfson Microelectronics plc

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