WM5102 datasheet(112/334 Pages) WOLFSON

112 / 334 page

WM5102

Production Data

PD, June 2014, Rev 4.2

112

only be set to ‘1’ when the applicable DCVDD condition is satisfied, as described in Table 97.

The clock source for the DSP block is enabled using DSP1_SYS_ENA. The clock must be enabled

before (or simultaneous to) enabling the DSP Core or DMA channels. The clock must be disabled

after (or simultaneous to) disabling the DSP Core and DMA channels.

The DSP Memory must be enabled for any functionality of the DSP, including any register read/write

operations associated with DSP firmware loading. The DSP Memory is controlled using

DSP1_MEM_ENA; this bit is enabled by default.

The DSP1_RAM_RDY status bits indicate when the DSP firmware memory registers are ready for

read/write access. The DSP memory should not be accessed until this bit has been set.

The DSP RAM Ready flags are inputs to the Interrupt control circuit and can be used to trigger an

interrupt event - see “Interrupts”.

The DSP RAM Ready flags can be output directly on a GPIO pin as an external indication of the DSP

RAM Status. See “General Purpose Input / Output” to configure a GPIO pin for this function.

The DSP memory contents are retained during Hardware Reset and Software Reset, provided

DCVDD is held above its reset threshold. The DSP memory contents are cleared in Sleep mode, or if

DCVDD falls below its Reset threshold. See the “Applications Information” section for a summary of

the WM5102 memory reset conditions.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4352

(1100h)

DSP1

Control 1

DSP1_MEM_EN

DSP1 Memory Control

0 = Disabled

1 = Enabled

The DSP1 Memory Control must be

enabled for DSP1 firmware register

access and also for firmware execution.

DSP1_SYS_ENA

DSP1 Clock Enable

0 = Disabled

1 = Enabled

The DSP1 Clock must be enabled for

DSP1 firmware register access, code

execution, or DMA operation.

The DSP1 Core must be reset

(DSP1_CORE_ENA=0), and all DMA

channels disabled, when disabling the

DSP1 Clock.

R4353

(1101h)

DSP1

Clocking 1

2:0

DSP1_CLK_SEL

[2:0]

000

DSP1 Clock Frequency Select

000 = 6.144MHz (5.6448MHz)

001 = 12.288MHz (11.2896MHz)

010 = 24.576MHz (22.5792MHz)

011 = 49.152MHz (45.1584MHz)

The DSP1 Clock must be less than or

equal to the SYSCLK frequency.

The frequencies in brackets apply for

44.1kHz-related sample rates only (ie.

SAMPLE_RATE_n = 01XXX).

R4356

(1104h)

DSP1

Status 1

DSP1_RAM_RDY

DSP1 Memory Status

0 = Not ready

1 = Ready

Note - DSP1 memory should not be

accessed until this bit has been set.

Table 25 DSP Clocking Control

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