WM5102 datasheet(174/334 Pages) WOLFSON

174 / 334 page

WM5102

Production Data

PD, June 2014, Rev 4.2

174

SPEAKER OUTPUTS (ANALOGUE)

The speaker driver outputs SPKOUTLP, SPKOUTLN, SPKOUTLP and SPKOUTLN provide two

differential (BTL) outputs suitable for direct connection to external loudspeakers. The integrated Class

D speaker driver provides high efficiency at large signal levels.

The speaker driver signal paths incorporate a boost function which shifts the signal levels between the

AVDD and SPKVDD voltage domains. The boost is pre-configured (+12dB) for the recommended

AVDD and SPKVDD operating voltages (see “Recommended Operating Conditions”).

Ultra-low leakage and high PSRR allow the speaker supply SPKVDD to be connected directly to a

lithium battery. Note that SPKVDDL powers the Left Speaker driver, and SPKVDDR powers the Right

Speaker driver; it is assumed that SPKVDDL = SPKVDDR = SPKVDD.

Note that SYSCLK must be present and enabled when using the Class D speaker output; see

“Clocking and Sample Rates” for details of SYSCLK and the associated register control fields.

The OUT4L and OUT4R output signal paths are associated with the analogue outputs SPKOUTLP,

SPKOUTLN, SPKOUTLP and SPKOUTLN.

The Class D speaker output is a pulse width modulated signal, and requires external filtering in order

to recreate the audio signal. With a suitable choice of external speakers, the speakers themselves can

provide the necessary filtering. See “Applications Information” for further information on Class D

speaker connections.

The external speaker connection is illustrated in Figure 58, assuming suitable speakers are chosen to

provide the PWM filtering.

Figure 58 Speaker Connection

SPEAKER OUTPUTS (DIGITAL PDM)

The WM5102 supports a two-channel Pulse Density Modulation (PDM) digital speaker interface; the

PDM outputs are associated with the OUT5L and OUT5R output signal paths.

The PDM digital speaker interface is illustrated in Figure 59.

The OUT5L and OUT5R output signal paths are interleaved on the SPKDAT output pin, and clocked

using SPKCLK.

Note that the PDM interface supports two different operating modes; these are selected using the

SPK1_FMT register bit. See “Signal Timing Requirements” for detailed timing information in both

modes.

When SPK1_FMT = 0 (Mode A), then the Left PDM channel is valid at the rising edge of SPKCLK; the

Right PDM channel is valid at the falling edge of SPKCLK.

When SPK1_FMT = 1 (Mode B), then the Left PDM channel is valid during the low phase of SPKCLK;

the Right PDM channel is valid during the high phase of SPKCLK.

WM5102 Datasheet(PDF) 174 Page - Wolfson Microelectronics plc