WM5102 datasheet(175/334 Pages) WOLFSON

175 / 334 page

Production Data

WM5102

PD, June 2014, Rev 4.2

175

Figure 59 Digital Speaker (PDM) Interface Timing

Clocking for the PDM interface is derived from SYSCLK. Note that the SYSCLK_ENA register must

also be set. See “Clocking and Sample Rates” for further details of the system clocks and control

registers.

When the OUT5L or OUT5R output signal path is enabled, the PDM interface clock signal is output on

the SPKCLK pin.

The output signal paths support normal and high performance operating modes, as described in the

“Output Signal Path” section. The SPKCLK frequency is set according to the operating mode of the

relevant output path, as described in Table 72.

Note that the SPKCLK frequencies noted in Table 72 assume that the SYSCLK frequency is a

multiple of 6.144MHz (SYSCLK_FRAC=0). If the SYSCLK frequency is a multiple of 5.6448MHz

(SYSCLK_FRAC=1), then the SPKCLK frequency will be scaled accordingly.

OUT5_OSR

DESCRIPTION

SPKCLK FREQUENCY

Normal mode

3.072MHz

High Performance mode

6.144MHz

Table 72 SPKCLK Frequency

The PDM output channels can be independently muted. When muted, the default output on each

channel is a DSD-compliant silent stream (0110_1001b). The mute output code can be programmed

to other values if required, using the SPK1_MUTE_SEQ register field. The mute output code can be

transmitted MSB-first or LSB-first; this is selectable using the SPK1_MUTE_ENDIAN register.

Note that the PDM Mute function is not a soft-mute; the audio output is interrupted immediately when

the PDM mute is asserted. It is recommended to use the Output Signal Path mute function before

applying the PDM mute. See Table 64 for details of the OUT5L_MUTE and OUT5R_MUTE registers.

The PDM output interface registers are described in Table 73.

WM5102 Datasheet(PDF) 175 Page - Wolfson Microelectronics plc