WM5102 datasheet(227/334 Pages) WOLFSON

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Production Data

WM5102

PD, June 2014, Rev 4.2

227

Sample Rate

SAMPLE_RATE_n

SYSCLK

Frequency

SYSCLK_FREQ

SYSCLK_FRAC

12kHz

24kHz

48kHz

96kHz

192kHz

4kHz

8kHz

16kHz

32kHz

01h

02h

03h

04h

05h

10h

11h

12h

13h

6.144MHz,

12.288MHz,

24.576MHz,

49.152MHz

000,

001,

010,

011

11.025kHz

22.05kHz

44.1kHz

88.2kHz

176.4kHz

09h

0Ah

0Bh

0Ch

0Dh

5.6448MHz,

11.2896MHz,

22.5792MHz,

45.1584MHz

000,

001,

010,

011

Note that each of the SAMPLE_RATE_n registers must select a sample rate value from the same

group in the two lists above.

Table 98 SYSCLK Frequency Selection

The required ASYNCCLK frequency is dependent on the ASYNC_SAMPLE_RATE_n registers. Table

99 illustrates the valid ASYNCCLK frequencies for every supported sample rate.

The ASYNC_CLK_FREQ register is used to identify the applicable ASYNCCLK frequency. It is

recommended that the highest possible ASYNCCLK frequency is selected.

Note that, if all the sample rates in the system are synchronised to SYSCLK, then the ASYNCCLK

may not be required at all. In this case, the ASYNCCLK should be disabled (see Table 100), and the

associated register values are not important.

Sample Rate

ASYNC_SAMPLE_RATE_n

ASYNCCLK

Frequency

ASYNC_CLK_FREQ

12kHz

24kHz

48kHz

96kHz

192kHz

4kHz

8kHz

16kHz

32kHz

01h

02h

03h

04h

05h

10h

11h

12h

13h

6.144MHz,

12.288MHz,

24.576MHz,

49.152MHz

000,

001,

010,

011

11.025kHz

22.05kHz

44.1kHz

88.2kHz

176.4kHz

09h

0Ah

0Bh

0Ch

0Dh

5.6448MHz,

11.2896MHz,

22.5792MHz

45.1584MHz

000,

001,

010,

011

Note that each of the ASYNC_SAMPLE_RATE_n registers must select a sample rate value from

the same group in the two lists above.

Table 99 ASYNCCLK Frequency Selection

The WM5102 supports automatic clocking configuration. The programmable dividers associated with

the ADCs, DACs and all DSP functions are configured automatically, with values determined from the

SYSCLK_FREQ, SAMPLE_RATE_n, ASYNC_CLK_FREQ and ASYNC_SAMPLE_RATE_n fields.

Note that the digital audio interface (AIF) clocking rates must be configured separately.

The sample rates of each AIF, the input (ADC) paths, output (DAC) paths and DSP functions are

selected as described in the respective sections. Stereo full-duplex sample rate conversion is

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