WM5102 datasheet(224/334 Pages) WOLFSON

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WM5102

Production Data

PD, June 2014, Rev 4.2

224

CLOCKING AND SAMPLE RATES

The WM5102 requires a clock reference for its internal functions and also for the input (ADC) paths,

output (DAC) paths and digital audio interfaces. Under typical clocking configurations, all commonly-

used audio sample rates can be derived directly from the external reference; for additional flexibility,

the WM5102 incorporates two Frequency Locked Loop (FLL) circuits to perform frequency conversion

and filtering.

External clock signals may be connected via MCLK1 and MCLK2. (These inputs are referenced to the

DBVDD1 power domain.) In AIF Slave modes, the BCLK signals may be used as a reference for the

system clocks. The SLIMbus interface can provide the clock reference, when used as the input to one

of the FLLs. To avoid audible glitches, all clock configurations must be set up before enabling

playback.

SYSTEM CLOCKING

The WM5102 supports two independent clock domains, referenced to the SYSCLK and ASYNCCLK

system clocks respectively.

Up to five different sample rates may be independently selected for specific audio interfaces and other

input/output signal paths. Each selected sample rate must be synchronised either to SYSCLK or to

ASYNCCLK, as described later.

The two system clocks are independent (ie. not synchronised). Stereo full-duplex sample rate

conversion is supported, allowing asynchronous audio data to be mixed and to be routed between

independent interfaces. See “Digital Core” for further details.

Each subsystem within the WM5102 digital core is clocked at a dynamically-controlled rate, limited by

the SYSCLK (or ASYNCCLK) frequency, as applicable. For maximum signal mixing and processing

capacity, it is recommended that the highest possible SYSCLK and ASYNCCLK frequencies are

configured.

If the SUBSYS_MAX_FREQ bit is set to ‘0’, then the digital core clocking rate is restricted to a

maximum of 24.576MHz (or 22.5792MHz), even if a higher system clock frequency is configured.

The maximum digital core clocking rates of 49.152MHz (or 45.1584MHz) are only supported when

SUBSYS_MAX_FREQ is set to ‘1’, and the DCVDD voltage is 1.8V (nominal).

See “Recommended Operating Conditions” for details of the DCVDD operating conditions. Note that,

if DCVDD is less than the minimum level for >24.576MHz clocking, then SUBSYS_MAX_FREQ must

be set to ‘0’.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R353

(0161h)

Dynamic

Frequency

Scaling 1

SUBSYS_MAX_F

REQ

Digital Core Clocking Limit

Sets the maximum digital core clocking

rate. The higher rate should only be

selected when the DCVDD voltage is

1.8V (nominal).

0 = 24.576MHz (22.5792MHz)

1 = 49.152MHz (45.1584MHz)

Table 97 System Clocking

WM5102 Datasheet(PDF) 224 Page - Wolfson Microelectronics plc

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