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WM5102 Datasheet(PDF) 222 Page - Wolfson Microelectronics plc |
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WM5102 Datasheet(HTML) 222 Page - Wolfson Microelectronics plc |
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222 / 334 page ![]() WM5102 Production Data w PD, June 2014, Rev 4.2 222 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 5 AIF2_ASYNC_O VERCLOCKED_ STS 0 4 AIF1_ASYNC_O VERCLOCKED_ STS 0 3 AIF3_SYNC_OV ERCLOCKED_ST S 0 2 AIF2_SYNC_OV ERCLOCKED_ST S 0 1 AIF1_SYNC_OV ERCLOCKED_ST S 0 0 PAD_CTRL_OVE RCLOCKED_STS 0 R3365 (0D25h) Interrupt Raw Status 7 15 SLIMBUS_SUBS YS_OVERCLOC KED_STS 0 Indicates an Overclocked Error condition for each respective sub-system. The bits are coded as: 0 = Normal 1 = Overclocked The OVERCLOCKED_STS bit will be asserted whenever any of these register bits is asserted. 14 SLIMBUS_ASYN C_OVERCLOCK ED_STS 0 13 SLIMBUS_SYNC _OVERCLOCKE D_STS 0 12 ASRC_ASYNC_S YS_OVERCLOC KED_STS 0 11 ASRC_ASYNC_ WARP_OVERCL OCKED_STS 0 10 ASRC_SYNC_SY S_OVERCLOCK ED_STS 0 9 ASRC_SYNC_W ARP_OVERCLO CKED_STS 0 3 DSP1_OVERCLO CKED_STS 0 1 ISRC2_OVERCL OCKED_STS 0 0 ISRC1_OVERCL OCKED_STS 0 R3366 (0D26h) Interrupt Raw Status 8 10 AIF3_UNDERCL OCKED_STS 0 Indicates an Underclocked Error condition for each respective sub- system. The bits are coded as: 0 = Normal 1 = Overclocked The UNDERCLOCKED_STS bit will be asserted whenever any of these register bits is asserted. 9 AIF2_UNDERCL OCKED_STS 0 8 AIF1_UNDERCL OCKED_STS 0 6 ISRC2_UNDERC LOCKED_STS 0 5 ISRC1_UNDERC LOCKED_STS 0 4 FX_UNDERCLO CKED_STS 0 3 ASRC_UNDERC LOCKED_STS 0 |
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